Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
23 * turns the edge mask and level mask registers into CPU0 edge
24 * mask/level mask registers, and adds CPU1 edge mask/level mask
26 * - the armadaxp variant for Armada XP systems. This variant keeps
27 * the normal cause/edge mask/level mask registers when the global
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
78 /* The MV78200 has per-CPU registers for edge mask and level mask */
83 * The Armada XP has per-CPU registers for interrupt cause, interrupt
99 u32 offset; member
114 u32 offset; member
139 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_cause() argument
143 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_cause()
147 *map = mvchip->regs; in mvebu_gpioreg_edge_cause()
148 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; in mvebu_gpioreg_edge_cause()
152 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_cause()
153 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_cause()
164 unsigned int offset; in mvebu_gpio_read_edge_cause() local
167 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_read_edge_cause()
168 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_cause()
177 unsigned int offset; in mvebu_gpio_write_edge_cause() local
179 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_write_edge_cause()
180 regmap_write(map, offset, val); in mvebu_gpio_write_edge_cause()
185 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_mask() argument
189 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_mask()
192 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
193 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; in mvebu_gpioreg_edge_mask()
197 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
198 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_edge_mask()
202 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_mask()
203 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_mask()
214 unsigned int offset; in mvebu_gpio_read_edge_mask() local
217 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_read_edge_mask()
218 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_mask()
227 unsigned int offset; in mvebu_gpio_write_edge_mask() local
229 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_write_edge_mask()
230 regmap_write(map, offset, val); in mvebu_gpio_write_edge_mask()
235 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_level_mask() argument
239 switch (mvchip->soc_variant) { in mvebu_gpioreg_level_mask()
242 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
243 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; in mvebu_gpioreg_level_mask()
247 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
248 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_level_mask()
252 *map = mvchip->percpu_regs; in mvebu_gpioreg_level_mask()
253 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_level_mask()
264 unsigned int offset; in mvebu_gpio_read_level_mask() local
267 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_read_level_mask()
268 regmap_read(map, offset, &val); in mvebu_gpio_read_level_mask()
277 unsigned int offset; in mvebu_gpio_write_level_mask() local
279 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_write_level_mask()
280 regmap_write(map, offset, val); in mvebu_gpio_write_level_mask()
289 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; in mvebu_pwmreg_blink_on_duration()
294 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; in mvebu_pwmreg_blink_off_duration()
304 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_set()
313 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get()
318 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, in mvebu_gpio_get()
320 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_get()
324 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); in mvebu_gpio_get()
335 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_blink()
352 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_input()
375 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_output()
386 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get_direction()
398 return irq_create_mapping(mvchip->domain, pin); in mvebu_gpio_to_irq()
407 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_ack()
408 u32 mask = d->mask; in mvebu_gpio_irq_ack()
418 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_mask()
420 u32 mask = d->mask; in mvebu_gpio_edge_irq_mask()
423 ct->mask_cache_priv &= ~mask; in mvebu_gpio_edge_irq_mask()
424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_mask()
431 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_unmask()
433 u32 mask = d->mask; in mvebu_gpio_edge_irq_unmask()
437 ct->mask_cache_priv |= mask; in mvebu_gpio_edge_irq_unmask()
438 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_unmask()
445 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_mask()
447 u32 mask = d->mask; in mvebu_gpio_level_irq_mask()
450 ct->mask_cache_priv &= ~mask; in mvebu_gpio_level_irq_mask()
451 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_mask()
458 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_unmask()
460 u32 mask = d->mask; in mvebu_gpio_level_irq_unmask()
463 ct->mask_cache_priv |= mask; in mvebu_gpio_level_irq_unmask()
464 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_unmask()
476 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
478 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
486 * EDGE cause mask
487 * data-in /--------| |-----| |----\
488 * -----| |----- ---- to main cause reg
489 * X \----------------| |----/
498 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_set_type()
502 pin = d->hwirq; in mvebu_gpio_irq_set_type()
504 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_irq_set_type()
506 return -EINVAL; in mvebu_gpio_irq_set_type()
510 return -EINVAL; in mvebu_gpio_irq_set_type()
513 if (!(ct->type & type)) in mvebu_gpio_irq_set_type()
515 return -EINVAL; in mvebu_gpio_irq_set_type()
523 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
524 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
529 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
530 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
536 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
537 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_irq_set_type()
538 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
539 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_set_type()
549 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
550 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
570 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_handler()
577 for (i = 0; i < mvchip->chip.ngpio; i++) { in mvebu_gpio_irq_handler()
580 irq = irq_find_mapping(mvchip->domain, i); in mvebu_gpio_irq_handler()
590 regmap_read(mvchip->regs, in mvebu_gpio_irq_handler()
591 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
594 regmap_write(mvchip->regs, in mvebu_gpio_irq_handler()
595 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
623 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_request()
628 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_request()
630 if (mvpwm->gpiod) { in mvebu_pwm_request()
631 ret = -EBUSY; in mvebu_pwm_request()
633 desc = gpiochip_request_own_desc(&mvchip->chip, in mvebu_pwm_request()
634 pwm->hwpwm, "mvebu-pwm", in mvebu_pwm_request()
642 mvpwm->gpiod = desc; in mvebu_pwm_request()
645 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_request()
654 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_free()
655 gpiochip_free_own_desc(mvpwm->gpiod); in mvebu_pwm_free()
656 mvpwm->gpiod = NULL; in mvebu_pwm_free()
657 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_free()
666 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_get_state()
671 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_get_state()
673 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); in mvebu_pwm_get_state()
679 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, in mvebu_pwm_get_state()
680 mvpwm->clk_rate); in mvebu_pwm_get_state()
682 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); in mvebu_pwm_get_state()
688 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); in mvebu_pwm_get_state()
690 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); in mvebu_pwm_get_state()
692 state->enabled = true; in mvebu_pwm_get_state()
694 state->enabled = false; in mvebu_pwm_get_state()
696 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_get_state()
705 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_apply()
710 if (state->polarity != PWM_POLARITY_NORMAL) in mvebu_pwm_apply()
711 return -EINVAL; in mvebu_pwm_apply()
713 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; in mvebu_pwm_apply()
716 return -EINVAL; in mvebu_pwm_apply()
728 val = (unsigned long long) mvpwm->clk_rate * state->period; in mvebu_pwm_apply()
730 val -= on; in mvebu_pwm_apply()
732 return -EINVAL; in mvebu_pwm_apply()
740 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_apply()
742 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); in mvebu_pwm_apply()
743 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); in mvebu_pwm_apply()
744 if (state->enabled) in mvebu_pwm_apply()
745 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); in mvebu_pwm_apply()
747 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); in mvebu_pwm_apply()
749 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_apply()
763 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_suspend()
765 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_suspend()
766 &mvpwm->blink_select); in mvebu_pwm_suspend()
767 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), in mvebu_pwm_suspend()
768 &mvpwm->blink_on_duration); in mvebu_pwm_suspend()
769 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), in mvebu_pwm_suspend()
770 &mvpwm->blink_off_duration); in mvebu_pwm_suspend()
775 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_resume()
777 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_resume()
778 mvpwm->blink_select); in mvebu_pwm_resume()
779 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), in mvebu_pwm_resume()
780 mvpwm->blink_on_duration); in mvebu_pwm_resume()
781 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), in mvebu_pwm_resume()
782 mvpwm->blink_off_duration); in mvebu_pwm_resume()
789 struct device *dev = &pdev->dev; in mvebu_pwm_probe()
793 u32 offset; in mvebu_pwm_probe() local
796 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
797 int ret = of_property_read_u32(dev->of_node, in mvebu_pwm_probe()
798 "marvell,pwm-offset", &offset); in mvebu_pwm_probe()
810 offset = 0; in mvebu_pwm_probe()
813 if (IS_ERR(mvchip->clk)) in mvebu_pwm_probe()
814 return PTR_ERR(mvchip->clk); in mvebu_pwm_probe()
816 chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm)); in mvebu_pwm_probe()
821 mvchip->mvpwm = mvpwm; in mvebu_pwm_probe()
822 mvpwm->mvchip = mvchip; in mvebu_pwm_probe()
823 mvpwm->offset = offset; in mvebu_pwm_probe()
825 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
826 mvpwm->regs = mvchip->regs; in mvebu_pwm_probe()
828 switch (mvchip->offset) { in mvebu_pwm_probe()
837 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; in mvebu_pwm_probe()
840 return -EINVAL; in mvebu_pwm_probe()
847 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_pwm_probe()
849 if (IS_ERR(mvpwm->regs)) in mvebu_pwm_probe()
850 return PTR_ERR(mvpwm->regs); in mvebu_pwm_probe()
861 return -EINVAL; in mvebu_pwm_probe()
864 regmap_write(mvchip->regs, in mvebu_pwm_probe()
865 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); in mvebu_pwm_probe()
867 mvpwm->clk_rate = clk_get_rate(mvchip->clk); in mvebu_pwm_probe()
868 if (!mvpwm->clk_rate) { in mvebu_pwm_probe()
870 return -EINVAL; in mvebu_pwm_probe()
873 chip->ops = &mvebu_pwm_ops; in mvebu_pwm_probe()
875 spin_lock_init(&mvpwm->lock); in mvebu_pwm_probe()
890 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); in mvebu_gpio_dbg_show()
891 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); in mvebu_gpio_dbg_show()
892 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); in mvebu_gpio_dbg_show()
893 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_dbg_show()
894 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_dbg_show()
906 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); in mvebu_gpio_dbg_show()
915 seq_printf(s, " in %s (act %s) - IRQ", in mvebu_gpio_dbg_show()
923 seq_puts(s, " edge "); in mvebu_gpio_dbg_show()
935 .compatible = "marvell,orion-gpio",
939 .compatible = "marvell,mv78200-gpio",
943 .compatible = "marvell,armadaxp-gpio",
947 .compatible = "marvell,armada-370-gpio",
951 .compatible = "marvell,armada-8k-gpio",
964 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_suspend()
965 &mvchip->out_reg); in mvebu_gpio_suspend()
966 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_suspend()
967 &mvchip->io_conf_reg); in mvebu_gpio_suspend()
968 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_suspend()
969 &mvchip->blink_en_reg); in mvebu_gpio_suspend()
970 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_suspend()
971 &mvchip->in_pol_reg); in mvebu_gpio_suspend()
973 switch (mvchip->soc_variant) { in mvebu_gpio_suspend()
976 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
977 &mvchip->edge_mask_regs[0]); in mvebu_gpio_suspend()
978 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
979 &mvchip->level_mask_regs[0]); in mvebu_gpio_suspend()
983 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
985 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
986 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
988 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
993 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
995 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
996 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
998 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
1016 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_resume()
1017 mvchip->out_reg); in mvebu_gpio_resume()
1018 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_resume()
1019 mvchip->io_conf_reg); in mvebu_gpio_resume()
1020 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_resume()
1021 mvchip->blink_en_reg); in mvebu_gpio_resume()
1022 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_resume()
1023 mvchip->in_pol_reg); in mvebu_gpio_resume()
1025 switch (mvchip->soc_variant) { in mvebu_gpio_resume()
1028 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1029 mvchip->edge_mask_regs[0]); in mvebu_gpio_resume()
1030 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1031 mvchip->level_mask_regs[0]); in mvebu_gpio_resume()
1035 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1037 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1038 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1040 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1045 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1047 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1048 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1050 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1072 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1074 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_raw()
1075 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_raw()
1079 * registers, so no offset is needed. in mvebu_gpio_probe_raw()
1081 mvchip->offset = 0; in mvebu_gpio_probe_raw()
1085 * per-CPU registers in mvebu_gpio_probe_raw()
1087 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { in mvebu_gpio_probe_raw()
1092 mvchip->percpu_regs = in mvebu_gpio_probe_raw()
1093 devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1095 if (IS_ERR(mvchip->percpu_regs)) in mvebu_gpio_probe_raw()
1096 return PTR_ERR(mvchip->percpu_regs); in mvebu_gpio_probe_raw()
1105 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); in mvebu_gpio_probe_syscon()
1106 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_syscon()
1107 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_syscon()
1109 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) in mvebu_gpio_probe_syscon()
1110 return -EINVAL; in mvebu_gpio_probe_syscon()
1125 struct device_node *np = pdev->dev.of_node; in mvebu_gpio_probe()
1134 soc_variant = (unsigned long)device_get_match_data(&pdev->dev); in mvebu_gpio_probe()
1143 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), in mvebu_gpio_probe()
1146 return -ENOMEM; in mvebu_gpio_probe()
1150 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { in mvebu_gpio_probe()
1151 dev_err(&pdev->dev, "Missing ngpios OF property\n"); in mvebu_gpio_probe()
1152 return -ENODEV; in mvebu_gpio_probe()
1155 id = of_alias_get_id(pdev->dev.of_node, "gpio"); in mvebu_gpio_probe()
1157 dev_err(&pdev->dev, "Couldn't get OF id\n"); in mvebu_gpio_probe()
1161 mvchip->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_gpio_probe()
1163 if (!IS_ERR(mvchip->clk)) in mvebu_gpio_probe()
1164 clk_prepare_enable(mvchip->clk); in mvebu_gpio_probe()
1166 mvchip->soc_variant = soc_variant; in mvebu_gpio_probe()
1167 mvchip->chip.label = dev_name(&pdev->dev); in mvebu_gpio_probe()
1168 mvchip->chip.parent = &pdev->dev; in mvebu_gpio_probe()
1169 mvchip->chip.request = gpiochip_generic_request; in mvebu_gpio_probe()
1170 mvchip->chip.free = gpiochip_generic_free; in mvebu_gpio_probe()
1171 mvchip->chip.get_direction = mvebu_gpio_get_direction; in mvebu_gpio_probe()
1172 mvchip->chip.direction_input = mvebu_gpio_direction_input; in mvebu_gpio_probe()
1173 mvchip->chip.get = mvebu_gpio_get; in mvebu_gpio_probe()
1174 mvchip->chip.direction_output = mvebu_gpio_direction_output; in mvebu_gpio_probe()
1175 mvchip->chip.set = mvebu_gpio_set; in mvebu_gpio_probe()
1177 mvchip->chip.to_irq = mvebu_gpio_to_irq; in mvebu_gpio_probe()
1178 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; in mvebu_gpio_probe()
1179 mvchip->chip.ngpio = ngpios; in mvebu_gpio_probe()
1180 mvchip->chip.can_sleep = false; in mvebu_gpio_probe()
1181 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; in mvebu_gpio_probe()
1197 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1198 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1199 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1200 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1201 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1202 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1205 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1207 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1209 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1214 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1215 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); in mvebu_gpio_probe()
1216 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); in mvebu_gpio_probe()
1218 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1220 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1222 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1230 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); in mvebu_gpio_probe()
1243 mvchip->domain = in mvebu_gpio_probe()
1245 if (!mvchip->domain) { in mvebu_gpio_probe()
1246 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", in mvebu_gpio_probe()
1247 mvchip->chip.label); in mvebu_gpio_probe()
1248 return -ENODEV; in mvebu_gpio_probe()
1251 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, in mvebu_gpio_probe()
1252 mvchip->domain); in mvebu_gpio_probe()
1257 mvchip->domain, ngpios, 2, np->name, handle_level_irq, in mvebu_gpio_probe()
1260 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", in mvebu_gpio_probe()
1261 mvchip->chip.label); in mvebu_gpio_probe()
1269 gc = irq_get_domain_generic_chip(mvchip->domain, 0); in mvebu_gpio_probe()
1270 gc->private = mvchip; in mvebu_gpio_probe()
1271 ct = &gc->chip_types[0]; in mvebu_gpio_probe()
1272 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in mvebu_gpio_probe()
1273 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; in mvebu_gpio_probe()
1274 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; in mvebu_gpio_probe()
1275 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1276 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1278 ct = &gc->chip_types[1]; in mvebu_gpio_probe()
1279 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; in mvebu_gpio_probe()
1280 ct->chip.irq_ack = mvebu_gpio_irq_ack; in mvebu_gpio_probe()
1281 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; in mvebu_gpio_probe()
1282 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; in mvebu_gpio_probe()
1283 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1284 ct->handler = handle_edge_irq; in mvebu_gpio_probe()
1285 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1306 .name = "mvebu-gpio",