Lines Matching +full:control +full:- +full:parent
1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
43 * Clock output control register defines.
55 * struct ixp4xx_gpio - IXP4 GPIO state container
58 * @base: remapped I/O-memory base
59 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
74 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
82 gpiochip_disable_irq(gc, d->hwirq); in ixp4xx_gpio_mask_irq()
90 /* ACK when unmasking if not edge-triggered */ in ixp4xx_gpio_irq_unmask()
91 if (!(g->irq_edge & BIT(d->hwirq))) in ixp4xx_gpio_irq_unmask()
94 gpiochip_enable_irq(gc, d->hwirq); in ixp4xx_gpio_irq_unmask()
102 int line = d->hwirq; in ixp4xx_gpio_irq_set_type()
112 g->irq_edge |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
117 g->irq_edge |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
122 g->irq_edge |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
127 g->irq_edge &= ~BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
132 g->irq_edge &= ~BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
135 return -EINVAL; in ixp4xx_gpio_irq_set_type()
139 /* pins 8-15 */ in ixp4xx_gpio_irq_set_type()
140 line -= 8; in ixp4xx_gpio_irq_set_type()
143 /* pins 0-7 */ in ixp4xx_gpio_irq_set_type()
147 raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags); in ixp4xx_gpio_irq_set_type()
150 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type()
152 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type()
154 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_set_type()
157 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type()
159 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type()
161 /* Force-configure this line as an input */ in ixp4xx_gpio_irq_set_type()
162 val = __raw_readl(g->base + IXP4XX_REG_GPOE); in ixp4xx_gpio_irq_set_type()
163 val |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
164 __raw_writel(val, g->base + IXP4XX_REG_GPOE); in ixp4xx_gpio_irq_set_type()
166 raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); in ixp4xx_gpio_irq_set_type()
168 /* This parent only accept level high (asserted) */ in ixp4xx_gpio_irq_set_type()
185 unsigned int *parent, in ixp4xx_gpio_child_to_parent_hwirq() argument
193 *parent = 6; in ixp4xx_gpio_child_to_parent_hwirq()
197 *parent = 7; in ixp4xx_gpio_child_to_parent_hwirq()
201 *parent = child + 17; in ixp4xx_gpio_child_to_parent_hwirq()
204 return -EINVAL; in ixp4xx_gpio_child_to_parent_hwirq()
210 struct device *dev = &pdev->dev; in ixp4xx_gpio_probe()
211 struct device_node *np = dev->of_node; in ixp4xx_gpio_probe()
212 struct irq_domain *parent; in ixp4xx_gpio_probe() local
222 return -ENOMEM; in ixp4xx_gpio_probe()
223 g->dev = dev; in ixp4xx_gpio_probe()
225 g->base = devm_platform_ioremap_resource(pdev, 0); in ixp4xx_gpio_probe()
226 if (IS_ERR(g->base)) in ixp4xx_gpio_probe()
227 return PTR_ERR(g->base); in ixp4xx_gpio_probe()
231 dev_err(dev, "no IRQ parent node\n"); in ixp4xx_gpio_probe()
232 return -ENODEV; in ixp4xx_gpio_probe()
234 parent = irq_find_host(irq_parent); in ixp4xx_gpio_probe()
235 if (!parent) { in ixp4xx_gpio_probe()
236 dev_err(dev, "no IRQ parent domain\n"); in ixp4xx_gpio_probe()
237 return -ENODEV; in ixp4xx_gpio_probe()
242 * we take full control of the clock by masking off all bits for in ixp4xx_gpio_probe()
243 * the clock control and selectively enabling them. Otherwise in ixp4xx_gpio_probe()
247 * If you need control over TC and DC, add these to the device in ixp4xx_gpio_probe()
250 clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout"); in ixp4xx_gpio_probe()
251 clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout"); in ixp4xx_gpio_probe()
257 if (of_machine_is_compatible("dlink,dsm-g600-a") || in ixp4xx_gpio_probe()
258 of_machine_is_compatible("iom,nas-100d")) in ixp4xx_gpio_probe()
261 val = __raw_readl(g->base + IXP4XX_REG_GPCLK); in ixp4xx_gpio_probe()
281 __raw_writel(val, g->base + IXP4XX_REG_GPCLK); in ixp4xx_gpio_probe()
284 * This is a very special big-endian ARM issue: when the IXP4xx is in ixp4xx_gpio_probe()
286 * around to the CPU-native endianness. As you see mostly in the in ixp4xx_gpio_probe()
299 ret = bgpio_init(&g->gc, dev, 4, in ixp4xx_gpio_probe()
300 g->base + IXP4XX_REG_GPIN, in ixp4xx_gpio_probe()
301 g->base + IXP4XX_REG_GPOUT, in ixp4xx_gpio_probe()
304 g->base + IXP4XX_REG_GPOE, in ixp4xx_gpio_probe()
310 g->gc.ngpio = 16; in ixp4xx_gpio_probe()
311 g->gc.label = "IXP4XX_GPIO_CHIP"; in ixp4xx_gpio_probe()
314 * are fetched using phandles, set this to -1 to get rid of in ixp4xx_gpio_probe()
317 g->gc.base = 0; in ixp4xx_gpio_probe()
318 g->gc.parent = &pdev->dev; in ixp4xx_gpio_probe()
319 g->gc.owner = THIS_MODULE; in ixp4xx_gpio_probe()
321 girq = &g->gc.irq; in ixp4xx_gpio_probe()
323 girq->fwnode = dev_fwnode(dev); in ixp4xx_gpio_probe()
324 girq->parent_domain = parent; in ixp4xx_gpio_probe()
325 girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq; in ixp4xx_gpio_probe()
326 girq->handler = handle_bad_irq; in ixp4xx_gpio_probe()
327 girq->default_type = IRQ_TYPE_NONE; in ixp4xx_gpio_probe()
329 ret = devm_gpiochip_add_data(dev, &g->gc, g); in ixp4xx_gpio_probe()
343 .compatible = "intel,ixp4xx-gpio",
351 .name = "ixp4xx-gpio",