59  * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
72 	struct ixp4xx_gpio *g = gpiochip_get_data(gc);  in ixp4xx_gpio_irq_ack()  local
74 	__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);  in ixp4xx_gpio_irq_ack()
88 	struct ixp4xx_gpio *g = gpiochip_get_data(gc);  in ixp4xx_gpio_irq_unmask()  local
91 	if (!(g->irq_edge & BIT(d->hwirq)))  in ixp4xx_gpio_irq_unmask()
101 	struct ixp4xx_gpio *g = gpiochip_get_data(gc);  in ixp4xx_gpio_irq_set_type()  local
112 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
117 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
122 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
127 		g->irq_edge &= ~BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
132 		g->irq_edge &= ~BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
147 	raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);  in ixp4xx_gpio_irq_set_type()
150 	val = __raw_readl(g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
152 	__raw_writel(val, g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
154 	__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);  in ixp4xx_gpio_irq_set_type()
157 	val = __raw_readl(g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
159 	__raw_writel(val, g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
162 	val = __raw_readl(g->base + IXP4XX_REG_GPOE);  in ixp4xx_gpio_irq_set_type()
164 	__raw_writel(val, g->base + IXP4XX_REG_GPOE);  in ixp4xx_gpio_irq_set_type()
166 	raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);  in ixp4xx_gpio_irq_set_type()
196 	if (child == 1) {  in ixp4xx_gpio_child_to_parent_hwirq()
213 	struct ixp4xx_gpio *g;  in ixp4xx_gpio_probe()  local
220 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);  in ixp4xx_gpio_probe()
221 	if (!g)  in ixp4xx_gpio_probe()
223 	g->dev = dev;  in ixp4xx_gpio_probe()
225 	g->base = devm_platform_ioremap_resource(pdev, 0);  in ixp4xx_gpio_probe()
226 	if (IS_ERR(g->base))  in ixp4xx_gpio_probe()
227 		return PTR_ERR(g->base);  in ixp4xx_gpio_probe()
261 		val = __raw_readl(g->base + IXP4XX_REG_GPCLK);  in ixp4xx_gpio_probe()
269 				val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);  in ixp4xx_gpio_probe()
275 				val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);  in ixp4xx_gpio_probe()
281 	__raw_writel(val, g->base + IXP4XX_REG_GPCLK);  in ixp4xx_gpio_probe()
299 	ret = bgpio_init(&g->gc, dev, 4,  in ixp4xx_gpio_probe()
300 			 g->base + IXP4XX_REG_GPIN,  in ixp4xx_gpio_probe()
301 			 g->base + IXP4XX_REG_GPOUT,  in ixp4xx_gpio_probe()
304 			 g->base + IXP4XX_REG_GPOE,  in ixp4xx_gpio_probe()
310 	g->gc.ngpio = 16;  in ixp4xx_gpio_probe()
311 	g->gc.label = "IXP4XX_GPIO_CHIP";  in ixp4xx_gpio_probe()
314 	 * are fetched using phandles, set this to -1 to get rid of  in ixp4xx_gpio_probe()
317 	g->gc.base = 0;  in ixp4xx_gpio_probe()
318 	g->gc.parent = &pdev->dev;  in ixp4xx_gpio_probe()
319 	g->gc.owner = THIS_MODULE;  in ixp4xx_gpio_probe()
321 	girq = &g->gc.irq;  in ixp4xx_gpio_probe()
329 	ret = devm_gpiochip_add_data(dev, &g->gc, g);  in ixp4xx_gpio_probe()
335 	platform_set_drvdata(pdev, g);  in ixp4xx_gpio_probe()