35 	struct ep93xx_gpio_irq_chip	*eic;  member
44 	return egc->eic;  in to_ep93xx_gpio_irq_chip()
58 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic)  in ep93xx_gpio_update_int_params()  argument
60 	writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);  in ep93xx_gpio_update_int_params()
62 	writeb_relaxed(eic->int_type2,  in ep93xx_gpio_update_int_params()
63 		       eic->base + EP93XX_INT_TYPE2_OFFSET);  in ep93xx_gpio_update_int_params()
65 	writeb_relaxed(eic->int_type1,  in ep93xx_gpio_update_int_params()
66 		       eic->base + EP93XX_INT_TYPE1_OFFSET);  in ep93xx_gpio_update_int_params()
68 	writeb_relaxed(eic->int_unmasked & eic->int_enabled,  in ep93xx_gpio_update_int_params()
69 		       eic->base + EP93XX_INT_EN_OFFSET);  in ep93xx_gpio_update_int_params()
75 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_int_debounce()  local
79 		eic->int_debounce |= port_mask;  in ep93xx_gpio_int_debounce()
81 		eic->int_debounce &= ~port_mask;  in ep93xx_gpio_int_debounce()
83 	writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET);  in ep93xx_gpio_int_debounce()
88 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_ab_irq_handler()  local
92 	stat = readb(eic->base + EP93XX_INT_STATUS_OFFSET);  in ep93xx_gpio_ab_irq_handler()
126 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_ack()  local
130 		eic->int_type2 ^= port_mask; /* switch edge direction */  in ep93xx_gpio_irq_ack()
131 		ep93xx_gpio_update_int_params(eic);  in ep93xx_gpio_irq_ack()
134 	writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);  in ep93xx_gpio_irq_ack()
140 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_mask_ack()  local
145 		eic->int_type2 ^= port_mask; /* switch edge direction */  in ep93xx_gpio_irq_mask_ack()
147 	eic->int_unmasked &= ~port_mask;  in ep93xx_gpio_irq_mask_ack()
148 	ep93xx_gpio_update_int_params(eic);  in ep93xx_gpio_irq_mask_ack()
150 	writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);  in ep93xx_gpio_irq_mask_ack()
157 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_mask()  local
160 	eic->int_unmasked &= ~BIT(hwirq);  in ep93xx_gpio_irq_mask()
161 	ep93xx_gpio_update_int_params(eic);  in ep93xx_gpio_irq_mask()
168 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_unmask()  local
172 	eic->int_unmasked |= BIT(hwirq);  in ep93xx_gpio_irq_unmask()
173 	ep93xx_gpio_update_int_params(eic);  in ep93xx_gpio_irq_unmask()
184 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_type()  local
193 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
194 		eic->int_type2 |= port_mask;  in ep93xx_gpio_irq_type()
198 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
199 		eic->int_type2 &= ~port_mask;  in ep93xx_gpio_irq_type()
203 		eic->int_type1 &= ~port_mask;  in ep93xx_gpio_irq_type()
204 		eic->int_type2 |= port_mask;  in ep93xx_gpio_irq_type()
208 		eic->int_type1 &= ~port_mask;  in ep93xx_gpio_irq_type()
209 		eic->int_type2 &= ~port_mask;  in ep93xx_gpio_irq_type()
213 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
216 			eic->int_type2 &= ~port_mask; /* falling */  in ep93xx_gpio_irq_type()
218 			eic->int_type2 |= port_mask; /* rising */  in ep93xx_gpio_irq_type()
227 	eic->int_enabled |= port_mask;  in ep93xx_gpio_irq_type()
229 	ep93xx_gpio_update_int_params(eic);  in ep93xx_gpio_irq_type()
256 	.name			= "ep93xx-gpio-eic",
281 	egc->eic = devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL);  in ep93xx_setup_irqs()
282 	if (!egc->eic)  in ep93xx_setup_irqs()
285 	egc->eic->base = intr;  in ep93xx_setup_irqs()