Lines Matching +full:gpio +full:- +full:dir
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DaVinci GPIO Support
5 * Copyright (c) 2006-2007 David Brownell
9 #include <linux/gpio/driver.h>
30 u32 dir; member
44 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
58 /* Serialize access to GPIO registers */
67 static inline u32 __gpio_mask(unsigned gpio) in __gpio_mask() argument
69 return 1 << (gpio % 32); in __gpio_mask()
83 /*--------------------------------------------------------------------------*/
85 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
96 g = d->regs[bank]; in __davinci_direction()
97 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
98 temp = readl_relaxed(&g->dir); in __davinci_direction()
101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
105 writel_relaxed(temp, &g->dir); in __davinci_direction()
106 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
126 * Note that changes are synched to the GPIO clock, so reading values back
135 g = d->regs[bank]; in davinci_gpio_get()
137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
141 * Assuming the pin is muxed as a gpio output, set its output value.
150 g = d->regs[bank]; in davinci_gpio_set()
153 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
161 struct device *dev = &pdev->dev; in davinci_gpio_probe()
165 * The gpio banks conceptually expose a segmented bitmap, in davinci_gpio_probe()
166 * and "ngpio" is one more than the largest zero-based in davinci_gpio_probe()
173 return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n"); in davinci_gpio_probe()
180 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", in davinci_gpio_probe()
192 return -EINVAL; in davinci_gpio_probe()
197 return -ENOMEM; in davinci_gpio_probe()
204 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
205 if (chips->irqs[i] < 0) in davinci_gpio_probe()
206 return chips->irqs[i]; in davinci_gpio_probe()
209 chips->chip.label = dev_name(dev); in davinci_gpio_probe()
211 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
212 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
213 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
214 chips->chip.set = davinci_gpio_set; in davinci_gpio_probe()
216 chips->chip.ngpio = ngpio; in davinci_gpio_probe()
217 chips->chip.base = -1; in davinci_gpio_probe()
220 chips->chip.parent = dev; in davinci_gpio_probe()
221 chips->chip.request = gpiochip_generic_request; in davinci_gpio_probe()
222 chips->chip.free = gpiochip_generic_free; in davinci_gpio_probe()
224 spin_lock_init(&chips->lock); in davinci_gpio_probe()
226 chips->gpio_unbanked = gpio_unbanked; in davinci_gpio_probe()
230 chips->regs[bank] = gpio_base + offset_array[bank]; in davinci_gpio_probe()
232 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); in davinci_gpio_probe()
244 /*--------------------------------------------------------------------------*/
261 writel_relaxed(mask, &g->clr_falling); in gpio_irq_mask()
262 writel_relaxed(mask, &g->clr_rising); in gpio_irq_mask()
276 writel_relaxed(mask, &g->set_falling); in gpio_irq_unmask()
278 writel_relaxed(mask, &g->set_rising); in gpio_irq_unmask()
284 return -EINVAL; in gpio_irq_type()
290 .name = "GPIO",
306 bank_num = irqdata->bank_num; in gpio_irq_handler()
307 g = irqdata->regs; in gpio_irq_handler()
308 d = irqdata->chip; in gpio_irq_handler()
322 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
325 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
337 generic_handle_domain_irq(d->irq_domain, hw_irq); in gpio_irq_handler()
341 /* now it may re-trigger */ in gpio_irq_handler()
348 if (d->irq_domain) in gpio_to_irq_banked()
349 return irq_create_mapping(d->irq_domain, offset); in gpio_to_irq_banked()
351 return -ENXIO; in gpio_to_irq_banked()
360 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
362 if (offset < d->gpio_unbanked) in gpio_to_irq_unbanked()
363 return d->irqs[offset]; in gpio_to_irq_unbanked()
365 return -ENODEV; in gpio_to_irq_unbanked()
375 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
377 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
381 return -EINVAL; in gpio_irq_type_unbanked()
386 return -EINVAL; in gpio_irq_type_unbanked()
389 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
391 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
401 (struct davinci_gpio_controller *)d->host_data; in davinci_gpio_irq_map()
402 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map()
447 unsigned gpio, bank; in davinci_gpio_irq_setup() local
452 struct device *dev = &pdev->dev; in davinci_gpio_irq_setup()
464 if (dev->of_node) in davinci_gpio_irq_setup()
467 ngpio = chips->chip.ngpio; in davinci_gpio_irq_setup()
469 clk = devm_clk_get_enabled(dev, "gpio"); in davinci_gpio_irq_setup()
471 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); in davinci_gpio_irq_setup()
475 if (!chips->gpio_unbanked) { in davinci_gpio_irq_setup()
476 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); in davinci_gpio_irq_setup()
482 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, in davinci_gpio_irq_setup()
487 return -ENODEV; in davinci_gpio_irq_setup()
493 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
497 chips->chip.to_irq = gpio_to_irq_banked; in davinci_gpio_irq_setup()
498 chips->irq_domain = irq_domain; in davinci_gpio_irq_setup()
501 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO in davinci_gpio_irq_setup()
505 if (chips->gpio_unbanked) { in davinci_gpio_irq_setup()
506 /* pass "bank 0" GPIO IRQs to AINTC */ in davinci_gpio_irq_setup()
507 chips->chip.to_irq = gpio_to_irq_unbanked; in davinci_gpio_irq_setup()
509 binten = GENMASK(chips->gpio_unbanked / 16, 0); in davinci_gpio_irq_setup()
511 /* AINTC handles mask/unmask; GPIO handles triggering */ in davinci_gpio_irq_setup()
512 irq = chips->irqs[0]; in davinci_gpio_irq_setup()
514 irq_chip->name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
515 irq_chip->irq_set_type = gpio_irq_type_unbanked; in davinci_gpio_irq_setup()
518 g = chips->regs[0]; in davinci_gpio_irq_setup()
519 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
520 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
523 for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) { in davinci_gpio_irq_setup()
524 irq_set_chip(chips->irqs[gpio], irq_chip); in davinci_gpio_irq_setup()
525 irq_set_handler_data(chips->irqs[gpio], chips); in davinci_gpio_irq_setup()
526 irq_set_status_flags(chips->irqs[gpio], in davinci_gpio_irq_setup()
534 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we in davinci_gpio_irq_setup()
537 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { in davinci_gpio_irq_setup()
542 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
543 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
544 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
548 * gpio irqs. Pass the irq bank's corresponding controller to in davinci_gpio_irq_setup()
551 irqdata = devm_kzalloc(&pdev->dev, in davinci_gpio_irq_setup()
556 return -ENOMEM; in davinci_gpio_irq_setup()
558 irqdata->regs = g; in davinci_gpio_irq_setup()
559 irqdata->bank_num = bank; in davinci_gpio_irq_setup()
560 irqdata->chip = chips; in davinci_gpio_irq_setup()
562 irq_set_chained_handler_and_data(chips->irqs[bank], in davinci_gpio_irq_setup()
570 * BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
586 base = chips->regs[0] - offset_array[0]; in davinci_gpio_save_context()
587 chips->binten_context = readl_relaxed(base + BINTEN); in davinci_gpio_save_context()
590 g = chips->regs[bank]; in davinci_gpio_save_context()
591 context = &chips->context[bank]; in davinci_gpio_save_context()
592 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
593 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
594 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
595 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
599 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
610 base = chips->regs[0] - offset_array[0]; in davinci_gpio_restore_context()
612 if (readl_relaxed(base + BINTEN) != chips->binten_context) in davinci_gpio_restore_context()
613 writel_relaxed(chips->binten_context, base + BINTEN); in davinci_gpio_restore_context()
616 g = chips->regs[bank]; in davinci_gpio_restore_context()
617 context = &chips->context[bank]; in davinci_gpio_restore_context()
618 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
619 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
620 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
621 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
622 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
623 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
624 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
625 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()
632 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); in davinci_gpio_suspend()
642 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); in davinci_gpio_resume()
653 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
654 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
655 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
670 * GPIO driver registration needs to be done before machine_init functions
671 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
686 MODULE_DESCRIPTION("DAVINCI GPIO driver");
688 MODULE_ALIAS("platform:gpio-davinci");