114 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)  in crystalcove_update_irq_mask()  argument
119 	if (cg->set_irq_mask)  in crystalcove_update_irq_mask()
120 		regmap_update_bits(cg->regmap, mirqs0, mask, mask);  in crystalcove_update_irq_mask()
122 		regmap_update_bits(cg->regmap, mirqs0, mask, 0);  in crystalcove_update_irq_mask()
125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)  in crystalcove_update_irq_ctrl()  argument
129 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);  in crystalcove_update_irq_ctrl()
134 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_dir_in()  local
140 	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);  in crystalcove_gpio_dir_in()
145 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_dir_out()  local
151 	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);  in crystalcove_gpio_dir_out()
156 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_get()  local
163 	ret = regmap_read(cg->regmap, reg, &val);  in crystalcove_gpio_get()
172 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_set()  local
179 		regmap_update_bits(cg->regmap, reg, 1, 1);  in crystalcove_gpio_set()
181 		regmap_update_bits(cg->regmap, reg, 1, 0);  in crystalcove_gpio_set()
186 	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));  in crystalcove_irq_type()  local
194 		cg->intcnt_value = CTLI_INTCNT_DIS;  in crystalcove_irq_type()
197 		cg->intcnt_value = CTLI_INTCNT_BE;  in crystalcove_irq_type()
200 		cg->intcnt_value = CTLI_INTCNT_PE;  in crystalcove_irq_type()
203 		cg->intcnt_value = CTLI_INTCNT_NE;  in crystalcove_irq_type()
209 	cg->update |= UPDATE_IRQ_TYPE;  in crystalcove_irq_type()
216 	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));  in crystalcove_bus_lock()  local
218 	mutex_lock(&cg->buslock);  in crystalcove_bus_lock()
223 	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));  in crystalcove_bus_sync_unlock()  local
226 	if (cg->update & UPDATE_IRQ_TYPE)  in crystalcove_bus_sync_unlock()
227 		crystalcove_update_irq_ctrl(cg, hwirq);  in crystalcove_bus_sync_unlock()
228 	if (cg->update & UPDATE_IRQ_MASK)  in crystalcove_bus_sync_unlock()
229 		crystalcove_update_irq_mask(cg, hwirq);  in crystalcove_bus_sync_unlock()
230 	cg->update = 0;  in crystalcove_bus_sync_unlock()
232 	mutex_unlock(&cg->buslock);  in crystalcove_bus_sync_unlock()
238 	struct crystalcove_gpio *cg = gpiochip_get_data(gc);  in crystalcove_irq_unmask()  local
246 	cg->set_irq_mask = false;  in crystalcove_irq_unmask()
247 	cg->update |= UPDATE_IRQ_MASK;  in crystalcove_irq_unmask()
253 	struct crystalcove_gpio *cg = gpiochip_get_data(gc);  in crystalcove_irq_mask()  local
259 	cg->set_irq_mask = true;  in crystalcove_irq_mask()
260 	cg->update |= UPDATE_IRQ_MASK;  in crystalcove_irq_mask()
278 	struct crystalcove_gpio *cg = data;  in crystalcove_gpio_irq_handler()  local
284 	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||  in crystalcove_gpio_irq_handler()
285 	    regmap_read(cg->regmap, GPIO1IRQ, &p1))  in crystalcove_gpio_irq_handler()
288 	regmap_write(cg->regmap, GPIO0IRQ, p0);  in crystalcove_gpio_irq_handler()
289 	regmap_write(cg->regmap, GPIO1IRQ, p1);  in crystalcove_gpio_irq_handler()
294 		virq = irq_find_mapping(cg->chip.irq.domain, gpio);  in crystalcove_gpio_irq_handler()
303 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_dbg_show()  local
308 		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);  in crystalcove_gpio_dbg_show()
309 		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);  in crystalcove_gpio_dbg_show()
310 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,  in crystalcove_gpio_dbg_show()
312 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,  in crystalcove_gpio_dbg_show()
314 		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,  in crystalcove_gpio_dbg_show()
333 	struct crystalcove_gpio *cg;  in crystalcove_gpio_probe()  local
342 	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);  in crystalcove_gpio_probe()
343 	if (!cg)  in crystalcove_gpio_probe()
346 	mutex_init(&cg->buslock);  in crystalcove_gpio_probe()
347 	cg->chip.label = KBUILD_MODNAME;  in crystalcove_gpio_probe()
348 	cg->chip.direction_input = crystalcove_gpio_dir_in;  in crystalcove_gpio_probe()
349 	cg->chip.direction_output = crystalcove_gpio_dir_out;  in crystalcove_gpio_probe()
350 	cg->chip.get = crystalcove_gpio_get;  in crystalcove_gpio_probe()
351 	cg->chip.set = crystalcove_gpio_set;  in crystalcove_gpio_probe()
352 	cg->chip.base = -1;  in crystalcove_gpio_probe()
353 	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;  in crystalcove_gpio_probe()
354 	cg->chip.can_sleep = true;  in crystalcove_gpio_probe()
355 	cg->chip.parent = dev;  in crystalcove_gpio_probe()
356 	cg->chip.dbg_show = crystalcove_gpio_dbg_show;  in crystalcove_gpio_probe()
357 	cg->regmap = pmic->regmap;  in crystalcove_gpio_probe()
359 	girq = &cg->chip.irq;  in crystalcove_gpio_probe()
371 					   IRQF_ONESHOT, KBUILD_MODNAME, cg);  in crystalcove_gpio_probe()
377 	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);  in crystalcove_gpio_probe()
382 	irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);  in crystalcove_gpio_probe()