39 	struct gpio_chip gc;  member
63 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)  in brcmstb_gpio_gc_to_priv()  argument
65 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_gc_to_priv()
74 	return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &  in __brcmstb_gpio_get_active_irqs()
75 	       bank->gc.read_reg(reg_base + GIO_MASK(bank->id));  in __brcmstb_gpio_get_active_irqs()
84 	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_get_active_irqs()
86 	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_get_active_irqs()
94 	return hwirq - bank->gc.offset;  in brcmstb_gpio_hwirq_to_offset()
100 	struct gpio_chip *gc = &bank->gc;  in brcmstb_gpio_set_imask()  local
106 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in brcmstb_gpio_set_imask()
107 	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));  in brcmstb_gpio_set_imask()
112 	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);  in brcmstb_gpio_set_imask()
113 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in brcmstb_gpio_set_imask()
116 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)  in brcmstb_gpio_to_irq()  argument
118 	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);  in brcmstb_gpio_to_irq()
120 	int hwirq = offset + gc->offset;  in brcmstb_gpio_to_irq()
131 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_mask()  local
132 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_mask()
139 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_unmask()  local
140 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_unmask()
147 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_ack()  local
148 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_ack()
152 	gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);  in brcmstb_gpio_irq_ack()
157 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_set_type()  local
158 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_set_type()
196 	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_irq_set_type()
198 	iedge_config = bank->gc.read_reg(priv->reg_base +  in brcmstb_gpio_irq_set_type()
200 	iedge_insensitive = bank->gc.read_reg(priv->reg_base +  in brcmstb_gpio_irq_set_type()
202 	ilevel = bank->gc.read_reg(priv->reg_base +  in brcmstb_gpio_irq_set_type()
205 	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),  in brcmstb_gpio_irq_set_type()
207 	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),  in brcmstb_gpio_irq_set_type()
209 	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),  in brcmstb_gpio_irq_set_type()
212 	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_irq_set_type()
233 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_set_wake()  local
234 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_set_wake()
265 	int hwbase = bank->gc.offset;  in brcmstb_gpio_irq_bank_handler()
305 		i += bank->gc.ngpio;  in brcmstb_gpio_hwirq_to_bank()
334 	ret = irq_set_chip_data(irq, &bank->gc);  in brcmstb_gpio_irq_map()
396 		gpiochip_remove(&bank->gc);  in brcmstb_gpio_remove()
399 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,  in brcmstb_gpio_of_xlate()  argument
402 	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);  in brcmstb_gpio_of_xlate()
403 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_of_xlate()
406 	if (gc->of_gpio_n_cells != 2) {  in brcmstb_gpio_of_xlate()
411 	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))  in brcmstb_gpio_of_xlate()
414 	offset = gpiospec->args[0] - bank->gc.offset;  in brcmstb_gpio_of_xlate()
415 	if (offset >= gc->ngpio || offset < 0)  in brcmstb_gpio_of_xlate()
497 	struct gpio_chip *gc = &bank->gc;  in brcmstb_gpio_bank_save()  local
501 		bank->saved_regs[i] = gc->read_reg(priv->reg_base +  in brcmstb_gpio_bank_save()
509 	struct gpio_chip *gc;  in brcmstb_gpio_quiesce()  local
517 		gc = &bank->gc;  in brcmstb_gpio_quiesce()
527 		gc->write_reg(priv->reg_base + GIO_MASK(bank->id),  in brcmstb_gpio_quiesce()
542 	struct gpio_chip *gc = &bank->gc;  in brcmstb_gpio_bank_restore()  local
546 		gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),  in brcmstb_gpio_bank_restore()
639 		struct gpio_chip *gc;  in brcmstb_gpio_probe()  local
673 		gc = &bank->gc;  in brcmstb_gpio_probe()
674 		err = bgpio_init(gc, dev, 4,  in brcmstb_gpio_probe()
683 		gc->owner = THIS_MODULE;  in brcmstb_gpio_probe()
684 		gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);  in brcmstb_gpio_probe()
685 		if (!gc->label) {  in brcmstb_gpio_probe()
689 		gc->of_gpio_n_cells = 2;  in brcmstb_gpio_probe()
690 		gc->of_xlate = brcmstb_gpio_of_xlate;  in brcmstb_gpio_probe()
692 		gc->ngpio = MAX_GPIO_PER_BANK;  in brcmstb_gpio_probe()
693 		gc->offset = bank->id * MAX_GPIO_PER_BANK;  in brcmstb_gpio_probe()
694 		gc->request = gpiochip_generic_request;  in brcmstb_gpio_probe()
695 		gc->free = gpiochip_generic_free;  in brcmstb_gpio_probe()
697 			gc->to_irq = brcmstb_gpio_to_irq;  in brcmstb_gpio_probe()
704 		gc->write_reg(reg_base + GIO_MASK(bank->id), 0);  in brcmstb_gpio_probe()
706 		err = gpiochip_add_data(gc, bank);  in brcmstb_gpio_probe()
712 		num_gpios += gc->ngpio;  in brcmstb_gpio_probe()
715 			gc->base, gc->ngpio, bank->width);  in brcmstb_gpio_probe()