215 	u32 intr_status;  in zynq_fpga_isr()  local
222 	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);  in zynq_fpga_isr()
223 	if (!(intr_status & IXR_ERROR_FLAGS_MASK) &&  in zynq_fpga_isr()
224 	    (intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {  in zynq_fpga_isr()
389 	u32 intr_status;  in zynq_fpga_ops_write()  local
438 	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);  in zynq_fpga_ops_write()
447 	if (intr_status & IXR_ERROR_FLAGS_MASK) {  in zynq_fpga_ops_write()
454 	    !((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {  in zynq_fpga_ops_write()
470 		intr_status,  in zynq_fpga_ops_write()
490 	u32 intr_status;  in zynq_fpga_ops_write_complete()  local
496 	err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,  in zynq_fpga_ops_write_complete()
497 				     intr_status & IXR_PCFG_DONE_MASK,  in zynq_fpga_ops_write_complete()
527 	u32 intr_status;  in zynq_fpga_ops_state()  local
536 	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);  in zynq_fpga_ops_state()
539 	if (intr_status & IXR_PCFG_DONE_MASK)  in zynq_fpga_ops_state()