18 #define SOCFPGA_FPGMGR_STAT_OFST				0x0
19 #define SOCFPGA_FPGMGR_CTL_OFST					0x4
20 #define SOCFPGA_FPGMGR_DCLKCNT_OFST				0x8
21 #define SOCFPGA_FPGMGR_DCLKSTAT_OFST				0xc
22 #define SOCFPGA_FPGMGR_GPIO_INTEN_OFST				0x830
23 #define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST				0x834
24 #define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST			0x838
25 #define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST			0x83c
26 #define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST			0x840
27 #define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST			0x844
28 #define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST			0x84c
29 #define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST			0x850
33 #define SOCFPGA_FPGMGR_STAT_POWER_UP				0x0 /*ramping*/
34 #define SOCFPGA_FPGMGR_STAT_RESET				0x1
35 #define SOCFPGA_FPGMGR_STAT_CFG					0x2
36 #define SOCFPGA_FPGMGR_STAT_INIT				0x3
37 #define SOCFPGA_FPGMGR_STAT_USER_MODE				0x4
38 #define SOCFPGA_FPGMGR_STAT_UNKNOWN				0x5
39 #define SOCFPGA_FPGMGR_STAT_STATE_MASK				0x7
41 #define SOCFPGA_FPGMGR_STAT_POWER_OFF				0x0
43 #define MSEL_PP16_FAST_NOAES_NODC				0x0
44 #define MSEL_PP16_FAST_AES_NODC					0x1
45 #define MSEL_PP16_FAST_AESOPT_DC				0x2
46 #define MSEL_PP16_SLOW_NOAES_NODC				0x4
47 #define MSEL_PP16_SLOW_AES_NODC					0x5
48 #define MSEL_PP16_SLOW_AESOPT_DC				0x6
49 #define MSEL_PP32_FAST_NOAES_NODC				0x8
50 #define MSEL_PP32_FAST_AES_NODC					0x9
51 #define MSEL_PP32_FAST_AESOPT_DC				0xa
52 #define MSEL_PP32_SLOW_NOAES_NODC				0xc
53 #define MSEL_PP32_SLOW_AES_NODC					0xd
54 #define MSEL_PP32_SLOW_AESOPT_DC				0xe
55 #define SOCFPGA_FPGMGR_STAT_MSEL_MASK				0x000000f8
59 #define SOCFPGA_FPGMGR_CTL_EN					0x00000001
60 #define SOCFPGA_FPGMGR_CTL_NCE					0x00000002
61 #define SOCFPGA_FPGMGR_CTL_NCFGPULL				0x00000004
63 #define CDRATIO_X1						0x00000000
64 #define CDRATIO_X2						0x00000040
65 #define CDRATIO_X4						0x00000080
66 #define CDRATIO_X8						0x000000c0
67 #define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK				0x000000c0
69 #define SOCFPGA_FPGMGR_CTL_AXICFGEN				0x00000100
71 #define CFGWDTH_16						0x00000000
72 #define CFGWDTH_32						0x00000200
73 #define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK				0x00000200
76 #define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE			0x1
79 #define SOCFPGA_FPGMGR_MON_NSTATUS				0x0001
80 #define SOCFPGA_FPGMGR_MON_CONF_DONE				0x0002
81 #define SOCFPGA_FPGMGR_MON_INIT_DONE				0x0004
82 #define SOCFPGA_FPGMGR_MON_CRC_ERROR				0x0008
83 #define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE			0x0010
84 #define SOCFPGA_FPGMGR_MON_PR_READY				0x0020
85 #define SOCFPGA_FPGMGR_MON_PR_ERROR				0x0040
86 #define SOCFPGA_FPGMGR_MON_PR_DONE				0x0080
87 #define SOCFPGA_FPGMGR_MON_NCONFIG_PIN				0x0100
88 #define SOCFPGA_FPGMGR_MON_NSTATUS_PIN				0x0200
89 #define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN			0x0400
90 #define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON			0x0800
91 #define SOCFPGA_FPGMGR_MON_STATUS_MASK				0x0fff
192 	if ((status & SOCFPGA_FPGMGR_MON_FPGA_POWER_ON) == 0)  in socfpga_fpga_state_get()
227 			return 0;  in socfpga_fpga_dclk_set_and_wait_clear()
245 		if ((socfpga_fpga_state_get(priv) & state) != 0)  in socfpga_fpga_wait_for_state()
246 			return 0;  in socfpga_fpga_wait_for_state()
256 	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST, 0);  in socfpga_fpga_enable_irqs()
265 	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTMSK_OFST, 0);  in socfpga_fpga_enable_irqs()
273 	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);  in socfpga_fpga_disable_irqs()
288 	conf_done = (st & SOCFPGA_FPGMGR_MON_CONF_DONE) != 0;  in socfpga_fpga_isr()
289 	nstatus = (st & SOCFPGA_FPGMGR_MON_NSTATUS) != 0;  in socfpga_fpga_isr()
295 					SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);  in socfpga_fpga_isr()
304 	int ret = 0;  in socfpga_fpga_wait_for_config_done()
314 	if (time_left == 0)  in socfpga_fpga_wait_for_config_done()
343 	if (mode < 0)  in socfpga_fpga_cfg_mode_set()
352 	/* Set NCE to 0. */  in socfpga_fpga_cfg_mode_set()
356 	return 0;  in socfpga_fpga_cfg_mode_set()
368 	 *  - Set CTRL.NCE to 0  in socfpga_fpga_reset()
386 	/* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */  in socfpga_fpga_reset()
394 	return 0;  in socfpga_fpga_reset()
428 	return 0;  in socfpga_fpga_ops_configure_init()
439 	size_t i = 0;  in socfpga_fpga_ops_configure_write()
441 	if (count <= 0)  in socfpga_fpga_ops_configure_write()
453 		socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x00ffffff);  in socfpga_fpga_ops_configure_write()
456 		socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x0000ffff);  in socfpga_fpga_ops_configure_write()
459 		socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x000000ff);  in socfpga_fpga_ops_configure_write()
461 	case 0:  in socfpga_fpga_ops_configure_write()
468 	return 0;  in socfpga_fpga_ops_configure_write()
481 	 *  - if CONF_DONE = 0 and nSTATUS = 0, configuration failed  in socfpga_fpga_ops_configure_complete()
504 	/* Step 14: Set CTRL.EN to 0 */  in socfpga_fpga_ops_configure_complete()
508 	return 0;  in socfpga_fpga_ops_configure_complete()
555 	priv->fpga_base_addr = devm_platform_ioremap_resource(pdev, 0);  in socfpga_fpga_probe()
563 	priv->irq = platform_get_irq(pdev, 0);  in socfpga_fpga_probe()
564 	if (priv->irq < 0)  in socfpga_fpga_probe()
567 	ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0,  in socfpga_fpga_probe()