1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/fpga/fpga-mgr.h>
21 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
34 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_state()
36 	return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :  in ice40_fpga_ops_state()
44 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_write_init()
45 	struct spi_device *dev = priv->dev;  in ice40_fpga_ops_write_init()
62 	if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {  in ice40_fpga_ops_write_init()
63 		dev_err(&dev->dev,  in ice40_fpga_ops_write_init()
65 		return -ENOTSUPP;  in ice40_fpga_ops_write_init()
68 	/* Lock the bus, assert CRESET_B and SS_B and delay >200ns */  in ice40_fpga_ops_write_init()
69 	spi_bus_lock(dev->controller);  in ice40_fpga_ops_write_init()
71 	gpiod_set_value(priv->reset, 1);  in ice40_fpga_ops_write_init()
78 	gpiod_set_value(priv->reset, 0);  in ice40_fpga_ops_write_init()
80 	/* Abort if the chip-select failed */  in ice40_fpga_ops_write_init()
84 	/* Check CDONE is de-asserted i.e. the FPGA is reset */  in ice40_fpga_ops_write_init()
85 	if (gpiod_get_value(priv->cdone)) {  in ice40_fpga_ops_write_init()
86 		dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");  in ice40_fpga_ops_write_init()
87 		ret = -EIO;  in ice40_fpga_ops_write_init()
97 	spi_bus_unlock(dev->controller);  in ice40_fpga_ops_write_init()
105 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_write()
107 	return spi_write(priv->dev, buf, count);  in ice40_fpga_ops_write()
113 	struct ice40_fpga_priv *priv = mgr->priv;  in ice40_fpga_ops_write_complete()
114 	struct spi_device *dev = priv->dev;  in ice40_fpga_ops_write_complete()
118 	if (!gpiod_get_value(priv->cdone)) {  in ice40_fpga_ops_write_complete()
119 		dev_err(&dev->dev,  in ice40_fpga_ops_write_complete()
120 			"CDONE was not asserted after firmware transfer\n");  in ice40_fpga_ops_write_complete()
121 		return -EIO;  in ice40_fpga_ops_write_complete()
124 	/* Send of zero-padding to activate the firmware */  in ice40_fpga_ops_write_complete()
137 	struct device *dev = &spi->dev;  in ice40_fpga_probe()
142 	priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);  in ice40_fpga_probe()
144 		return -ENOMEM;  in ice40_fpga_probe()
146 	priv->dev = spi;  in ice40_fpga_probe()
149 	if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {  in ice40_fpga_probe()
152 		return -EINVAL;  in ice40_fpga_probe()
155 	if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {  in ice40_fpga_probe()
158 		return -EINVAL;  in ice40_fpga_probe()
161 	if (spi->mode & SPI_CPHA) {  in ice40_fpga_probe()
163 		return -EINVAL;  in ice40_fpga_probe()
167 	priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);  in ice40_fpga_probe()
168 	if (IS_ERR(priv->cdone)) {  in ice40_fpga_probe()
169 		ret = PTR_ERR(priv->cdone);  in ice40_fpga_probe()
174 	priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);  in ice40_fpga_probe()
175 	if (IS_ERR(priv->reset)) {  in ice40_fpga_probe()
176 		ret = PTR_ERR(priv->reset);  in ice40_fpga_probe()
187 	{ .compatible = "lattice,ice40-fpga-mgr", },
193 	{ .name = "ice40-fpga-mgr", },