drivers/fpga/dfl.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  * Copyright (C) 2017-2018 Intel Corporation, Inc.
24 #include <linux/io-64-nonatomic-lo-hi.h>
29 #include <linux/fpga/fpga-region.h>
31 /* maximum supported number of ports */
36 /* Reserved 0xfe for Header Group Register and 0xff for AFU */
89 #define DFHv1_CSR_SIZE_GRP	0x20  /* Size of Reg Block and Group/tag */
94  * 1'b1 = absolute (ARM or other non-PCIe use)
103 #define DFHv1_CSR_SIZE_GRP_GROUPING_ID	GENMASK_ULL(30, 16)	/* Group Features/interfaces */
105 #define DFHv1_CSR_SIZE_GRP_SIZE		GENMASK_ULL(63, 32)	/* Size of CSR Block in bytes */
139 #define FME_CAP_NUM_PORTS	GENMASK_ULL(19, 17)	/* Number of ports */
149 /* AFU MMIO access permission. 1 - VF, 0 - PF. */
210  * struct dfl_fpga_port_ops - port ops
233  * struct dfl_feature_id - dfl private feature id
242  * struct dfl_feature_driver - dfl private feature driver
253  * struct dfl_feature_irq_ctx - dfl private feature interrupt context
266  * struct dfl_feature - sub feature of the feature devices
300 #define FEATURE_DEV_ID_UNUSED	(-1)
303  * struct dfl_feature_platform_data - platform data for feature devices
311  * @disable_count: count for port disable.
313  * @open_count: count for feature device open.
337 	if (pdata->excl_open)  in dfl_feature_dev_use_begin()
338 		return -EBUSY;  in dfl_feature_dev_use_begin()
341 		if (pdata->open_count)  in dfl_feature_dev_use_begin()
342 			return -EBUSY;  in dfl_feature_dev_use_begin()
344 		pdata->excl_open = true;  in dfl_feature_dev_use_begin()
346 	pdata->open_count++;  in dfl_feature_dev_use_begin()
354 	pdata->excl_open = false;  in dfl_feature_dev_use_end()
356 	if (WARN_ON(pdata->open_count <= 0))  in dfl_feature_dev_use_end()
359 	pdata->open_count--;  in dfl_feature_dev_use_end()
365 	return pdata->open_count;  in dfl_feature_dev_use_count()
372 	pdata->private = private;  in dfl_fpga_pdata_set_private()
378 	return pdata->private;  in dfl_fpga_pdata_get_private()
389 #define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
390 #define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"
406 	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,  in dfl_fpga_inode_to_feature_dev()
408 	return pdata->dev;  in dfl_fpga_inode_to_feature_dev()
412 	for ((feature) = (pdata)->features;				    \
413 	   (feature) < (pdata)->features + (pdata)->num; (feature)++)
422 		if (feature->id == id)  in dfl_get_feature_by_id()
433 	if (feature && feature->ioaddr)  in dfl_get_feature_ioaddr_by_id()
434 		return feature->ioaddr;  in dfl_get_feature_ioaddr_by_id()
443 	return pdata->dev->dev.parent->parent;  in dfl_fpga_pdata_to_parent()
468  * struct dfl_fpga_enum_info - DFL FPGA enumeration information
483  * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
503  * struct dfl_fpga_cdev - container device of DFL based FPGA
540 	mutex_lock(&cdev->lock);  in dfl_fpga_cdev_find_port()
542 	mutex_unlock(&cdev->lock);  in dfl_fpga_cdev_find_port()
552 			      unsigned int count, int32_t *fds);