1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2017-2018 Intel Corporation, Inc.
8  *   Zhang Yi <Yi.Z.Zhang@intel.com>
9  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
10  *   Joseph Grecco <joe.grecco@intel.com>
11  *   Enno Luebbers <enno.luebbers@intel.com>
12  *   Tim Whisonant <tim.whisonant@intel.com>
13  *   Ananda Ravuri <ananda.ravuri@intel.com>
14  *   Henry Mitchel <henry.mitchel@intel.com>
18 #include <linux/dma-mapping.h>
28 #define DRV_NAME	"dfl-pci"
55 		dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");  in cci_pci_alloc_irq()
127 	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);  in cci_init_drvdata()
129 		return -ENOMEM;  in cci_init_drvdata()
141 	dfl_fpga_feature_devs_remove(drvdata->cdev);  in cci_remove_feature_devs()
162 	u32 bir, offset, dfl_cnt, dfl_res;  in find_dfls_by_vsec()  local
169 		dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);  in find_dfls_by_vsec()
170 		return -ENODEV;  in find_dfls_by_vsec()
176 		dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",  in find_dfls_by_vsec()
178 		return -EINVAL;  in find_dfls_by_vsec()
183 		dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",  in find_dfls_by_vsec()
185 		return -EINVAL;  in find_dfls_by_vsec()
194 			dev_err(&pcidev->dev, "%s bad bir number %d\n",  in find_dfls_by_vsec()
196 			return -EINVAL;  in find_dfls_by_vsec()
200 			dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",  in find_dfls_by_vsec()
202 			return -EINVAL;  in find_dfls_by_vsec()
208 		offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;  in find_dfls_by_vsec()
209 		if (offset >= len) {  in find_dfls_by_vsec()
210 			dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",  in find_dfls_by_vsec()
211 				__func__, offset, &len);  in find_dfls_by_vsec()
212 			return -EINVAL;  in find_dfls_by_vsec()
215 		dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);  in find_dfls_by_vsec()
217 		len -= offset;  in find_dfls_by_vsec()
219 		start = pci_resource_start(pcidev, bir) + offset;  in find_dfls_by_vsec()
227 /* default method of finding dfls starting at offset 0 of bar 0 */
234 	u32 offset;  in find_dfls_by_default()  local
240 		return -ENOMEM;  in find_dfls_by_default()
274 			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);  in find_dfls_by_default()
278 				dev_err(&pcidev->dev, "bad BAR %d for port %d\n",  in find_dfls_by_default()
280 				ret = -EINVAL;  in find_dfls_by_default()
284 			start = pci_resource_start(pcidev, bar) + offset;  in find_dfls_by_default()
285 			len = pci_resource_len(pcidev, bar) - offset;  in find_dfls_by_default()
295 		ret = -ENODEV;  in find_dfls_by_default()
314 	info = dfl_fpga_enum_info_alloc(&pcidev->dev);  in cci_enumerate_feature_devs()
316 		return -ENOMEM;  in cci_enumerate_feature_devs()
321 		dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);  in cci_enumerate_feature_devs()
327 			ret = -ENOMEM;  in cci_enumerate_feature_devs()
338 	if (ret == -ENODEV)  in cci_enumerate_feature_devs()
347 		dev_err(&pcidev->dev, "Enumeration failure\n");  in cci_enumerate_feature_devs()
352 	drvdata->cdev = cdev;  in cci_enumerate_feature_devs()
370 		dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);  in cci_pci_probe()
376 	ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64));  in cci_pci_probe()
378 		ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32));  in cci_pci_probe()
380 		dev_err(&pcidev->dev, "No suitable DMA support available.\n");  in cci_pci_probe()
386 		dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);  in cci_pci_probe()
392 		dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);  in cci_pci_probe()
402 	struct dfl_fpga_cdev *cdev = drvdata->cdev;  in cci_pci_sriov_configure()
436 	if (dev_is_pf(&pcidev->dev))  in cci_pci_remove()