Lines Matching refs:FPGA

3 # FPGA framework configuration
6 menuconfig FPGA  config
7 	tristate "FPGA Configuration Framework"
10 	  kernel.  The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 	tristate "Altera SOCFPGA FPGA Manager"
19 	  FPGA manager driver support for Altera SOCFPGA.
26 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
41 	tristate "Altera FPGA Passive Serial over SPI"
45 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
49 	tristate "Altera CvP FPGA Manager"
52 	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
56 	tristate "Xilinx Zynq FPGA"
59 	  FPGA manager driver support for Xilinx Zynq FPGAs.
62 	tristate "Intel Stratix10 SoC FPGA Manager"
65 	  FPGA manager driver support for the Intel Stratix10 SoC.
75 	  FPGA manager driver support for Xilinx FPGA configuration
83 	  FPGA manager driver support for Xilinx FPGA configuration
90 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
96 	  FPGA manager driver support for Lattice MachXO2 configuration
100 	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
103 	  FPGA manager driver support for the Altera Cyclone II FPGA
107 	tristate "FPGA Bridge Framework"
113 	tristate "Altera SoCFPGA FPGA Bridges"
116 	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
120 	tristate "Altera FPGA Freeze Bridge"
123 	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
124 	  freeze bridge is a bridge that exists in the FPGA fabric to
125 	  isolate one region of the FPGA from the busses while that
135 	  The PR Decoupler exists in the FPGA fabric to isolate one
136 	  region of the FPGA from the busses while that region is
146 	tristate "FPGA Region"
149 	  FPGA Region common code.  An FPGA Region controls an FPGA Manager
150 	  and the FPGA Bridges associated with either a reconfigurable
151 	  region of an FPGA or a whole FPGA.
154 	tristate "FPGA Region Device Tree Overlay Support"
157 	  Support for loading FPGA images by applying a Device Tree
161 	tristate "FPGA Device Feature List (DFL) support"
168 	  to provide an extensible way of adding features for FPGA.
170 	  devices (e.g. FPGA Management Engine, Port and Accelerator
171 	  Function Unit) and their private features for target FPGA devices.
174 	  Gate Array (FPGA) solutions which implement Device Feature List.
178 	tristate "FPGA DFL FME Driver"
181 	  The FPGA Management Engine (FME) is a feature device implemented
184 	  FPGA platform level management features. There shall be one FME
185 	  per DFL based FPGA device.
188 	tristate "FPGA DFL FME Manager Driver"
191 	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
194 	tristate "FPGA DFL FME Bridge Driver"
197 	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
200 	tristate "FPGA DFL FME Region Driver"
203 	  Say Y to enable FPGA Region driver for FPGA Management Engine.
206 	tristate "FPGA DFL AFU Driver"
209 	  This is the driver for FPGA Accelerated Function Unit (AFU) which
211 	  to the FPGA infrastructure via a Port. There may be more than one
212 	  Port/AFU per DFL based FPGA device.
215 	tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
226 	tristate "FPGA DFL PCIe Device Driver"
230 	  Field-Programmable Gate Array (FPGA) solutions which implement
233 	  FPGA accelerators on the FPGA DFL devices, enables system level
234 	  management functions such as FPGA partial reconfiguration, power
241 	tristate "Xilinx ZynqMP FPGA"
244 	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
250 	tristate "Xilinx Versal FPGA"
253 	  Select this option to enable FPGA manager driver support for
270 	  the FPGA image, the Root Entry Hashes, etc.
273 	tristate "Microchip Polarfire SPI FPGA manager"
276 	  FPGA manager driver support for Microchip Polarfire FPGAs
284 	tristate "Lattice sysCONFIG SPI FPGA manager"
288 	  FPGA manager driver support for Lattice FPGAs programming over slave
293 endif # FPGA