Lines Matching refs:tegra_ivc_header_read_field

71 #define tegra_ivc_header_read_field(hdr, field) \  macro
102 	u32 tx = tegra_ivc_header_read_field(map, tx.count);  in tegra_ivc_empty()
103 	u32 rx = tegra_ivc_header_read_field(map, rx.count);  in tegra_ivc_empty()
123 	u32 tx = tegra_ivc_header_read_field(map, tx.count);  in tegra_ivc_full()
124 	u32 rx = tegra_ivc_header_read_field(map, rx.count);  in tegra_ivc_full()
135 	u32 tx = tegra_ivc_header_read_field(map, tx.count);  in tegra_ivc_available()
136 	u32 rx = tegra_ivc_header_read_field(map, rx.count);  in tegra_ivc_available()
149 	unsigned int count = tegra_ivc_header_read_field(&ivc->tx.map, tx.count);  in tegra_ivc_advance_tx()
161 	unsigned int count = tegra_ivc_header_read_field(&ivc->rx.map, rx.count);  in tegra_ivc_advance_rx()
184 	state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);  in tegra_ivc_check_read()
211 	state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);  in tegra_ivc_check_write()
435 	rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state);  in tegra_ivc_notified()
436 	tx_state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);  in tegra_ivc_notified()