Lines Matching +full:0 +full:x0000fc00
7 #define OHCI1394_Version 0x000
8 #define OHCI1394_GUID_ROM 0x004
9 #define OHCI1394_ATRetries 0x008
10 #define OHCI1394_CSRData 0x00C
11 #define OHCI1394_CSRCompareData 0x010
12 #define OHCI1394_CSRControl 0x014
13 #define OHCI1394_ConfigROMhdr 0x018
14 #define OHCI1394_BusID 0x01C
15 #define OHCI1394_BusOptions 0x020
16 #define OHCI1394_GUIDHi 0x024
17 #define OHCI1394_GUIDLo 0x028
18 #define OHCI1394_ConfigROMmap 0x034
19 #define OHCI1394_PostedWriteAddressLo 0x038
20 #define OHCI1394_PostedWriteAddressHi 0x03C
21 #define OHCI1394_VendorID 0x040
22 #define OHCI1394_HCControlSet 0x050
23 #define OHCI1394_HCControlClear 0x054
24 #define OHCI1394_HCControl_BIBimageValid 0x80000000
25 #define OHCI1394_HCControl_noByteSwapData 0x40000000
26 #define OHCI1394_HCControl_programPhyEnable 0x00800000
27 #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
28 #define OHCI1394_HCControl_LPS 0x00080000
29 #define OHCI1394_HCControl_postedWriteEnable 0x00040000
30 #define OHCI1394_HCControl_linkEnable 0x00020000
31 #define OHCI1394_HCControl_softReset 0x00010000
32 #define OHCI1394_SelfIDBuffer 0x064
33 #define OHCI1394_SelfIDCount 0x068
34 #define OHCI1394_IRMultiChanMaskHiSet 0x070
35 #define OHCI1394_IRMultiChanMaskHiClear 0x074
36 #define OHCI1394_IRMultiChanMaskLoSet 0x078
37 #define OHCI1394_IRMultiChanMaskLoClear 0x07C
38 #define OHCI1394_IntEventSet 0x080
39 #define OHCI1394_IntEventClear 0x084
40 #define OHCI1394_IntMaskSet 0x088
41 #define OHCI1394_IntMaskClear 0x08C
42 #define OHCI1394_IsoXmitIntEventSet 0x090
43 #define OHCI1394_IsoXmitIntEventClear 0x094
44 #define OHCI1394_IsoXmitIntMaskSet 0x098
45 #define OHCI1394_IsoXmitIntMaskClear 0x09C
46 #define OHCI1394_IsoRecvIntEventSet 0x0A0
47 #define OHCI1394_IsoRecvIntEventClear 0x0A4
48 #define OHCI1394_IsoRecvIntMaskSet 0x0A8
49 #define OHCI1394_IsoRecvIntMaskClear 0x0AC
50 #define OHCI1394_InitialBandwidthAvailable 0x0B0
51 #define OHCI1394_InitialChannelsAvailableHi 0x0B4
52 #define OHCI1394_InitialChannelsAvailableLo 0x0B8
53 #define OHCI1394_FairnessControl 0x0DC
54 #define OHCI1394_LinkControlSet 0x0E0
55 #define OHCI1394_LinkControlClear 0x0E4
61 #define OHCI1394_NodeID 0x0E8
62 #define OHCI1394_NodeID_idValid 0x80000000
63 #define OHCI1394_NodeID_root 0x40000000
64 #define OHCI1394_NodeID_nodeNumber 0x0000003f
65 #define OHCI1394_NodeID_busNumber 0x0000ffc0
66 #define OHCI1394_PhyControl 0x0EC
67 #define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000)
68 #define OHCI1394_PhyControl_ReadDone 0x80000000
69 #define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
70 #define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
71 #define OHCI1394_PhyControl_WritePending 0x00004000
72 #define OHCI1394_IsochronousCycleTimer 0x0F0
73 #define OHCI1394_AsReqFilterHiSet 0x100
74 #define OHCI1394_AsReqFilterHiClear 0x104
75 #define OHCI1394_AsReqFilterLoSet 0x108
76 #define OHCI1394_AsReqFilterLoClear 0x10C
77 #define OHCI1394_PhyReqFilterHiSet 0x110
78 #define OHCI1394_PhyReqFilterHiClear 0x114
79 #define OHCI1394_PhyReqFilterLoSet 0x118
80 #define OHCI1394_PhyReqFilterLoClear 0x11C
81 #define OHCI1394_PhyUpperBound 0x120
83 #define OHCI1394_AsReqTrContextBase 0x180
84 #define OHCI1394_AsReqTrContextControlSet 0x180
85 #define OHCI1394_AsReqTrContextControlClear 0x184
86 #define OHCI1394_AsReqTrCommandPtr 0x18C
88 #define OHCI1394_AsRspTrContextBase 0x1A0
89 #define OHCI1394_AsRspTrContextControlSet 0x1A0
90 #define OHCI1394_AsRspTrContextControlClear 0x1A4
91 #define OHCI1394_AsRspTrCommandPtr 0x1AC
93 #define OHCI1394_AsReqRcvContextBase 0x1C0
94 #define OHCI1394_AsReqRcvContextControlSet 0x1C0
95 #define OHCI1394_AsReqRcvContextControlClear 0x1C4
96 #define OHCI1394_AsReqRcvCommandPtr 0x1CC
98 #define OHCI1394_AsRspRcvContextBase 0x1E0
99 #define OHCI1394_AsRspRcvContextControlSet 0x1E0
100 #define OHCI1394_AsRspRcvContextControlClear 0x1E4
101 #define OHCI1394_AsRspRcvCommandPtr 0x1EC
104 #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
105 #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
106 #define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n))
107 #define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n))
110 #define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n))
111 #define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n))
112 #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
113 #define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n))
114 #define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
117 #define OHCI1394_reqTxComplete 0x00000001
118 #define OHCI1394_respTxComplete 0x00000002
119 #define OHCI1394_ARRQ 0x00000004
120 #define OHCI1394_ARRS 0x00000008
121 #define OHCI1394_RQPkt 0x00000010
122 #define OHCI1394_RSPkt 0x00000020
123 #define OHCI1394_isochTx 0x00000040
124 #define OHCI1394_isochRx 0x00000080
125 #define OHCI1394_postedWriteErr 0x00000100
126 #define OHCI1394_lockRespErr 0x00000200
127 #define OHCI1394_selfIDComplete 0x00010000
128 #define OHCI1394_busReset 0x00020000
129 #define OHCI1394_regAccessFail 0x00040000
130 #define OHCI1394_phy 0x00080000
131 #define OHCI1394_cycleSynch 0x00100000
132 #define OHCI1394_cycle64Seconds 0x00200000
133 #define OHCI1394_cycleLost 0x00400000
134 #define OHCI1394_cycleInconsistent 0x00800000
135 #define OHCI1394_unrecoverableError 0x01000000
136 #define OHCI1394_cycleTooLong 0x02000000
137 #define OHCI1394_phyRegRcvd 0x04000000
138 #define OHCI1394_masterIntEnable 0x80000000
140 #define OHCI1394_evt_no_status 0x0
141 #define OHCI1394_evt_long_packet 0x2
142 #define OHCI1394_evt_missing_ack 0x3
143 #define OHCI1394_evt_underrun 0x4
144 #define OHCI1394_evt_overrun 0x5
145 #define OHCI1394_evt_descriptor_read 0x6
146 #define OHCI1394_evt_data_read 0x7
147 #define OHCI1394_evt_data_write 0x8
148 #define OHCI1394_evt_bus_reset 0x9
149 #define OHCI1394_evt_timeout 0xa
150 #define OHCI1394_evt_tcode_err 0xb
151 #define OHCI1394_evt_reserved_b 0xc
152 #define OHCI1394_evt_reserved_c 0xd
153 #define OHCI1394_evt_unknown 0xe
154 #define OHCI1394_evt_flushed 0xf
162 #define OHCI1394_AT_DATA_Q0_srcBusID_MASK 0x00800000
164 #define OHCI1394_AT_DATA_Q0_spd_MASK 0x00070000
166 #define OHCI1394_AT_DATA_Q0_tLabel_MASK 0x0000fc00
168 #define OHCI1394_AT_DATA_Q0_rt_MASK 0x00000300
170 #define OHCI1394_AT_DATA_Q0_tCode_MASK 0x000000f0
172 #define OHCI1394_AT_DATA_Q1_destinationId_MASK 0xffff0000
174 #define OHCI1394_AT_DATA_Q1_destinationOffsetHigh_MASK 0x0000ffff
175 #define OHCI1394_AT_DATA_Q1_destinationOffsetHigh_SHIFT 0
176 #define OHCI1394_AT_DATA_Q1_rCode_MASK 0x0000f000
181 return !!((data[0] & OHCI1394_AT_DATA_Q0_srcBusID_MASK) >> OHCI1394_AT_DATA_Q0_srcBusID_SHIFT); in ohci1394_at_data_get_src_bus_id()
186 data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_srcBusID_MASK); in ohci1394_at_data_set_src_bus_id()
187 …data[0] |= cpu_to_le32((src_bus_id << OHCI1394_AT_DATA_Q0_srcBusID_SHIFT) & OHCI1394_AT_DATA_Q0_sr… in ohci1394_at_data_set_src_bus_id()
192 return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_spd_MASK) >> OHCI1394_AT_DATA_Q0_spd_SHIFT; in ohci1394_at_data_get_speed()
197 data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_spd_MASK); in ohci1394_at_data_set_speed()
198 data[0] |= cpu_to_le32((scode << OHCI1394_AT_DATA_Q0_spd_SHIFT) & OHCI1394_AT_DATA_Q0_spd_MASK); in ohci1394_at_data_set_speed()
203 …return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_tLabel_MASK) >> OHCI1394_AT_DATA_Q0_tLabel_SHIF… in ohci1394_at_data_get_tlabel()
208 data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_tLabel_MASK); in ohci1394_at_data_set_tlabel()
209 …data[0] |= cpu_to_le32((tlabel << OHCI1394_AT_DATA_Q0_tLabel_SHIFT) & OHCI1394_AT_DATA_Q0_tLabel_M… in ohci1394_at_data_set_tlabel()
214 return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_rt_MASK) >> OHCI1394_AT_DATA_Q0_rt_SHIFT; in ohci1394_at_data_get_retry()
219 data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_rt_MASK); in ohci1394_at_data_set_retry()
220 data[0] |= cpu_to_le32((retry << OHCI1394_AT_DATA_Q0_rt_SHIFT) & OHCI1394_AT_DATA_Q0_rt_MASK); in ohci1394_at_data_set_retry()
225 return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_tCode_MASK) >> OHCI1394_AT_DATA_Q0_tCode_SHIFT; in ohci1394_at_data_get_tcode()
230 data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_tCode_MASK); in ohci1394_at_data_set_tcode()
231 …data[0] |= cpu_to_le32((tcode << OHCI1394_AT_DATA_Q0_tCode_SHIFT) & OHCI1394_AT_DATA_Q0_tCode_MASK… in ohci1394_at_data_set_tcode()
255 u32 lo = (u32)(offset & 0x00000000ffffffff); in ohci1394_at_data_set_destination_offset()
277 #define OHCI1394_IT_DATA_Q0_spd_MASK 0x00070000
279 #define OHCI1394_IT_DATA_Q0_tag_MASK 0x0000c000
281 #define OHCI1394_IT_DATA_Q0_chanNum_MASK 0x00003f00
283 #define OHCI1394_IT_DATA_Q0_tcode_MASK 0x000000f0
285 #define OHCI1394_IT_DATA_Q0_sy_MASK 0x0000000f
286 #define OHCI1394_IT_DATA_Q0_sy_SHIFT 0
287 #define OHCI1394_IT_DATA_Q1_dataLength_MASK 0xffff0000
292 return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_spd_MASK) >> OHCI1394_IT_DATA_Q0_spd_SHIFT; in ohci1394_it_data_get_speed()
297 data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_spd_MASK); in ohci1394_it_data_set_speed()
298 data[0] |= cpu_to_le32((scode << OHCI1394_IT_DATA_Q0_spd_SHIFT) & OHCI1394_IT_DATA_Q0_spd_MASK); in ohci1394_it_data_set_speed()
303 return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_tag_MASK) >> OHCI1394_IT_DATA_Q0_tag_SHIFT; in ohci1394_it_data_get_tag()
308 data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_tag_MASK); in ohci1394_it_data_set_tag()
309 data[0] |= cpu_to_le32((tag << OHCI1394_IT_DATA_Q0_tag_SHIFT) & OHCI1394_IT_DATA_Q0_tag_MASK); in ohci1394_it_data_set_tag()
314 …return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_chanNum_MASK) >> OHCI1394_IT_DATA_Q0_chanNum_SH… in ohci1394_it_data_get_channel()
319 data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_chanNum_MASK); in ohci1394_it_data_set_channel()
320 …data[0] |= cpu_to_le32((channel << OHCI1394_IT_DATA_Q0_chanNum_SHIFT) & OHCI1394_IT_DATA_Q0_chanNu… in ohci1394_it_data_set_channel()
325 return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_tcode_MASK) >> OHCI1394_IT_DATA_Q0_tcode_SHIFT; in ohci1394_it_data_get_tcode()
330 data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_tcode_MASK); in ohci1394_it_data_set_tcode()
331 …data[0] |= cpu_to_le32((tcode << OHCI1394_IT_DATA_Q0_tcode_SHIFT) & OHCI1394_IT_DATA_Q0_tcode_MASK… in ohci1394_it_data_set_tcode()
336 return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_sy_MASK) >> OHCI1394_IT_DATA_Q0_sy_SHIFT; in ohci1394_it_data_get_sync()
341 data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_sy_MASK); in ohci1394_it_data_set_sync()
342 data[0] |= cpu_to_le32((sync << OHCI1394_IT_DATA_Q0_sy_SHIFT) & OHCI1394_IT_DATA_Q0_sy_MASK); in ohci1394_it_data_set_sync()
358 #define OHCI1394_SelfIDCount_selfIDError_MASK 0x80000000
360 #define OHCI1394_SelfIDCount_selfIDGeneration_MASK 0x00ff0000
362 #define OHCI1394_SelfIDCount_selfIDSize_MASK 0x000007fc
377 // additional first quadlet, since the field is 9 bits (0x1ff = 511).
383 #define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK 0x00ff0000
385 #define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK 0x0000ffff
386 #define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT 0