Lines Matching refs:dev_csr
1023 void __iomem *dev_csr; member
1061 l3cesr = readl(ctx->dev_csr + L3C_ESR); in xgene_edac_l3_check()
1070 l3celr = readl(ctx->dev_csr + L3C_ELR); in xgene_edac_l3_check()
1071 l3caelr = readl(ctx->dev_csr + L3C_AELR); in xgene_edac_l3_check()
1072 l3cbelr = readl(ctx->dev_csr + L3C_BELR); in xgene_edac_l3_check()
1100 writel(0, ctx->dev_csr + L3C_ESR); in xgene_edac_l3_check()
1119 val = readl(ctx->dev_csr + L3C_ECR); in xgene_edac_l3_hw_init()
1128 writel(val, ctx->dev_csr + L3C_ECR); in xgene_edac_l3_hw_init()
1154 writel(0xFFFFFFFF, ctx->dev_csr + L3C_ESR); in xgene_edac_l3_inject_ctrl_write()
1189 void __iomem *dev_csr; in xgene_edac_l3_add() local
1201 dev_csr = devm_ioremap_resource(edac->dev, &res); in xgene_edac_l3_add()
1202 if (IS_ERR(dev_csr)) { in xgene_edac_l3_add()
1205 rc = PTR_ERR(dev_csr); in xgene_edac_l3_add()
1218 ctx->dev_csr = dev_csr; in xgene_edac_l3_add()
1396 reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS); in xgene_edac_iob_gic_report()
1408 info = readl(ctx->dev_csr + XGICTRANSERRREQINFO); in xgene_edac_iob_gic_report()
1412 writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS); in xgene_edac_iob_gic_report()
1416 reg = readl(ctx->dev_csr + GLBL_ERR_STS); in xgene_edac_iob_gic_report()
1420 err_addr_lo = readl(ctx->dev_csr + GLBL_SEC_ERRL); in xgene_edac_iob_gic_report()
1421 err_addr_hi = readl(ctx->dev_csr + GLBL_SEC_ERRH); in xgene_edac_iob_gic_report()
1425 writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL); in xgene_edac_iob_gic_report()
1426 writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH); in xgene_edac_iob_gic_report()
1429 err_addr_lo = readl(ctx->dev_csr + GLBL_MSEC_ERRL); in xgene_edac_iob_gic_report()
1430 err_addr_hi = readl(ctx->dev_csr + GLBL_MSEC_ERRH); in xgene_edac_iob_gic_report()
1434 writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL); in xgene_edac_iob_gic_report()
1435 writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH); in xgene_edac_iob_gic_report()
1441 err_addr_lo = readl(ctx->dev_csr + GLBL_DED_ERRL); in xgene_edac_iob_gic_report()
1442 err_addr_hi = readl(ctx->dev_csr + GLBL_DED_ERRH); in xgene_edac_iob_gic_report()
1446 writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL); in xgene_edac_iob_gic_report()
1447 writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH); in xgene_edac_iob_gic_report()
1450 err_addr_lo = readl(ctx->dev_csr + GLBL_MDED_ERRL); in xgene_edac_iob_gic_report()
1451 err_addr_hi = readl(ctx->dev_csr + GLBL_MDED_ERRH); in xgene_edac_iob_gic_report()
1455 writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL); in xgene_edac_iob_gic_report()
1456 writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH); in xgene_edac_iob_gic_report()
1513 reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS); in xgene_edac_rb_report()
1560 err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL); in xgene_edac_rb_report()
1561 err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH); in xgene_edac_rb_report()
1567 readl(ctx->dev_csr + IOBBATRANSERRCSWREQID)); in xgene_edac_rb_report()
1568 writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS); in xgene_edac_rb_report()
1579 reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS); in xgene_edac_pa_report()
1602 writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS); in xgene_edac_pa_report()
1606 reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); in xgene_edac_pa_report()
1609 err_addr_lo = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOL); in xgene_edac_pa_report()
1610 err_addr_hi = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOH); in xgene_edac_pa_report()
1616 writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); in xgene_edac_pa_report()
1620 reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); in xgene_edac_pa_report()
1623 err_addr_lo = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOL); in xgene_edac_pa_report()
1624 err_addr_hi = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOH); in xgene_edac_pa_report()
1630 writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); in xgene_edac_pa_report()
1711 ctx->dev_csr + IOBAXIS0TRANSERRINTMSK); in xgene_edac_soc_hw_init()
1713 ctx->dev_csr + IOBAXIS1TRANSERRINTMSK); in xgene_edac_soc_hw_init()
1715 ctx->dev_csr + XGICTRANSERRINTMSK); in xgene_edac_soc_hw_init()
1727 void __iomem *dev_csr; in xgene_edac_soc_add() local
1740 dev_csr = devm_ioremap_resource(edac->dev, &res); in xgene_edac_soc_add()
1741 if (IS_ERR(dev_csr)) { in xgene_edac_soc_add()
1744 rc = PTR_ERR(dev_csr); in xgene_edac_soc_add()
1757 ctx->dev_csr = dev_csr; in xgene_edac_soc_add()