2  * Intel X38 Memory Controller kernel module
23 #define PCI_DEVICE_ID_INTEL_X38_HB	0x29e0
29 /* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
31 #define X38_MCHBAR_LOW	0x48	/* MCH Memory Mapped Register BAR */
32 #define X38_MCHBAR_HIGH	0x4c
33 #define X38_MCHBAR_MASK	0xfffffc000ULL	/* bits 35:14 */
36 #define X38_TOM	0xa0	/* Top of Memory (16b)
39 				 *  9:0  total populated physical memory
41 #define X38_TOM_MASK	0x3ff	/* bits 9:0 */
44 #define X38_ERRSTS	0xc8	/* Error Status Register (16b)
60 				 *  0    Single-bit DRAM ECC Error Flag (DSERR)
62 #define X38_ERRSTS_UE		0x0002
63 #define X38_ERRSTS_CE		0x0001
67 /* Intel  MMIO register space - device 0 function 0 - MMR space */
69 #define X38_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
72 				 *  9:0  Channel 0 DRAM Rank Boundary Address
74 #define X38_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
75 #define X38_DRB_MASK	0x3ff	/* bits 9:0 */
78 #define X38_C0ECCERRLOG 0x280	/* Channel 0 ECC Error Log (64b)
88 				 *    0  Correctable Error Status (CERRSTS)
90 #define X38_C1ECCERRLOG 0x680	/* Channel 1 ECC Error Log (64b) */
91 #define X38_ECCERRLOG_CE	0x1
92 #define X38_ECCERRLOG_UE	0x2
93 #define X38_ECCERRLOG_RANK_BITS	0x18000000
94 #define X38_ECCERRLOG_SYNDROME_BITS	0xff0000
96 #define X38_CAPID0 0xe0	/* see P.94 of spec for details */
105 	if (capid0_8b & 0x20) {	/* check DCD: Dual Channel Disable */  in how_many_channel()
106 		edac_dbg(0, "In single channel mode\n");  in how_many_channel()
109 		edac_dbg(0, "In dual channel mode\n");  in how_many_channel()
128 	X38 = 0,  enumerator
142 	[X38] = {
143 		.ctl_name = "x38"},
181 	info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);  in x38_get_and_clear_error_info()
194 		info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);  in x38_get_and_clear_error_info()
213 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,  in x38_process_error_info()
219 	for (channel = 0; channel < x38_channel_num; channel++) {  in x38_process_error_info()
223 					     0, 0, 0,  in x38_process_error_info()
226 					     "x38 UE", "");  in x38_process_error_info()
229 					     0, 0, eccerrlog_syndrome(log),  in x38_process_error_info()
232 					     "x38 CE", "");  in x38_process_error_info()
257 	pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1);  in x38_map_mchbar()
263 			"x38: mmio space beyond accessible range (0x%llx)\n",  in x38_map_mchbar()
270 		printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",  in x38_map_mchbar()
282 	for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {  in x38_get_drbs()
283 		drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;  in x38_get_drbs()
306 	if (rank > 0)  in drb_to_nr_pages()
310 		n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];  in drb_to_nr_pages()
327 	edac_dbg(0, "MC:\n");  in x38_probe1()
338 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in x38_probe1()
339 	layers[0].size = X38_RANKS;  in x38_probe1()
340 	layers[0].is_virt_csrow = true;  in x38_probe1()
344 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);  in x38_probe1()
371 	for (i = 0; i < mci->nr_csrows; i++) {  in x38_probe1()
379 		if (nr_pages == 0)  in x38_probe1()
382 		for (j = 0; j < x38_channel_num; j++) {  in x38_probe1()
403 	return 0;  in x38_probe1()
417 	edac_dbg(0, "MC:\n");  in x38_init_one()
419 	if (pci_enable_device(pdev) < 0)  in x38_init_one()
433 	edac_dbg(0, "\n");  in x38_remove_one()
446 	 PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
447 	 X38},
449 	 0,
450 	 }			/* 0 terminated list. */
472 	if (pci_rc < 0)  in x38_init()
476 		x38_registered = 0;  in x38_init()
480 			edac_dbg(0, "x38 pci_get_device fail\n");  in x38_init()
486 		if (pci_rc < 0) {  in x38_init()
487 			edac_dbg(0, "x38 init fail\n");  in x38_init()
493 	return 0;  in x38_init()
520 MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");
523 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");