Lines Matching refs:XDDR_PCSR_OFFSET
26 #define XDDR_PCSR_OFFSET 0xC macro
345 writel(PCSR_UNLOCK_VAL, ddrmc_base + XDDR_PCSR_OFFSET); in get_error_info()
353 writel(1, ddrmc_base + XDDR_PCSR_OFFSET); in get_error_info()
478 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in err_callback()
484 writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in err_callback()
646 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in enable_intr()
655 writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in enable_intr()
661 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in disable_intr()
668 writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in disable_intr()
798 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ce_store()
799 writel(PCSR_UNLOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ce_store()
807 writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ce_store()
808 writel(PCSR_LOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ce_store()
894 writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ue_store()
895 writel(PCSR_UNLOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ue_store()
902 writel(PCSR_LOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ue_store()
903 writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET); in inject_data_ue_store()