Lines Matching +full:interleave +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
24 #include <asm/intel-family.h>
70 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
71 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
72 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
73 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
74 0x100, 0x108, 0x110, 0x118, /* 20-23 */
107 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
108 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
109 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
110 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
111 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
146 int interleave) in sad_pkg() argument
148 return GET_BITFIELD(reg, table[interleave].start, in sad_pkg()
149 table[interleave].end); in sad_pkg()
207 /* Device 15, functions 2-5 */
253 /* Device 16, functions 2-7 */
293 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
488 /* Optional, mode 2HA */
515 * - 1 IMC
516 * - 3 DDR3 channels, 2 DPC per channel
518 * - 1 or 2 IMC
519 * - 4 DDR4 channels, 3 DPC per channel
521 * - 2 IMC
522 * - 4 DDR4 channels, 3 DPC per channel
524 * - 2 IMC
525 * - each IMC interfaces with a SMI 2 channel
526 * - each SMI channel interfaces with a scalable memory buffer
527 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
591 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
593 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
595 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
597 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
599 /* SAD target - 1-29-1 (1 of these) */
603 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
632 * - 1 IMC
633 * - 2 DDR3 channels, 2 DPC per channel
635 * - 1 or 2 IMC
636 * - 4 DDR4 channels, 3 DPC per channel
638 * - 2 IMC
639 * - 4 DDR4 channels, 3 DPC per channel
641 * - 2 IMC
642 * - each IMC interfaces with a SMI 2 channel
643 * - each SMI channel interfaces with a scalable memory buffer
644 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
710 return -EINVAL; in numrank()
723 return -EINVAL; in numrow()
736 return -EINVAL; in numcol()
757 sbridge_dev = list_entry(prev ? prev->list.next in get_sbridge_dev()
761 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && in get_sbridge_dev()
762 (dom == SOCK || dom == sbridge_dev->dom)) in get_sbridge_dev()
778 sbridge_dev->pdev = kcalloc(table->n_devs_per_imc, in alloc_sbridge_dev()
779 sizeof(*sbridge_dev->pdev), in alloc_sbridge_dev()
781 if (!sbridge_dev->pdev) { in alloc_sbridge_dev()
786 sbridge_dev->seg = seg; in alloc_sbridge_dev()
787 sbridge_dev->bus = bus; in alloc_sbridge_dev()
788 sbridge_dev->dom = dom; in alloc_sbridge_dev()
789 sbridge_dev->n_devs = table->n_devs_per_imc; in alloc_sbridge_dev()
790 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); in alloc_sbridge_dev()
797 list_del(&sbridge_dev->list); in free_sbridge_dev()
798 kfree(sbridge_dev->pdev); in free_sbridge_dev()
807 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
815 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
823 pci_read_config_dword(pvt->pci_br1, TOLM, ®); in ibridge_get_tolm()
832 pci_read_config_dword(pvt->pci_br1, TOHM, ®); in ibridge_get_tohm()
890 if (pvt->pci_ddrio) { in get_memory_type()
891 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, in get_memory_type()
910 if (!pvt->pci_ddrio) in haswell_get_memory_type()
913 pci_read_config_dword(pvt->pci_ddrio, in haswell_get_memory_type()
919 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); in haswell_get_memory_type()
991 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); in get_node_id()
999 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in haswell_get_node_id()
1007 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in knl_get_node_id()
1024 * home agent bank (7, 8), or one of the per-channel memory
1031 return bank - 7; in ibridge_get_ha()
1033 return (bank - 9) / 4; in ibridge_get_ha()
1049 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); in haswell_get_tolm()
1058 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); in haswell_get_tohm()
1060 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); in haswell_get_tohm()
1070 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); in knl_get_tolm()
1079 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); in knl_get_tohm()
1080 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); in knl_get_tohm()
1088 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; in haswell_rir_limit()
1148 * @ways: output number of interleave ways
1167 pci_mc = pvt->knl.pci_mc0; in knl_get_tad()
1170 pci_mc = pvt->knl.pci_mc1; in knl_get_tad()
1174 return -EINVAL; in knl_get_tad()
1186 return -ENODEV; in knl_get_tad()
1197 return -ENODEV; in knl_get_tad()
1222 * (This is the per-tile mapping of logical interleave targets to
1243 * (This is the per-tile mapping of logical interleave targets to
1271 * Render the EDC_ROUTE register in human-readable form.
1280 s[i*2+1] = '-'; in knl_show_edc_route()
1283 s[KNL_MAX_EDCS*2 - 1] = '\0'; in knl_show_edc_route()
1287 * Render the MC_ROUTE register in human-readable form.
1296 s[i*2+1] = '-'; in knl_show_mc_route()
1299 s[KNL_MAX_CHANNELS*2 - 1] = '\0'; in knl_show_mc_route()
1305 /* Is this dram rule backed by regular DRAM in flat mode? */
1324 * have to figure this out from the SAD rules, interleave lists, route tables,
1327 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1343 * only work in flat mode, not in cache mode.
1375 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1378 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { in knl_get_dimm_capacity()
1379 knl_show_edc_route(edc_route_reg[i-1], in knl_get_dimm_capacity()
1381 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1385 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1386 cur_reg_start, i-1, edc_route_string); in knl_get_dimm_capacity()
1390 knl_show_edc_route(edc_route_reg[i-1], edc_route_string); in knl_get_dimm_capacity()
1391 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1395 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1396 cur_reg_start, i-1, edc_route_string); in knl_get_dimm_capacity()
1401 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1404 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { in knl_get_dimm_capacity()
1405 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); in knl_get_dimm_capacity()
1406 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1410 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1411 cur_reg_start, i-1, mc_route_string); in knl_get_dimm_capacity()
1415 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); in knl_get_dimm_capacity()
1416 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1420 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1421 cur_reg_start, i-1, mc_route_string); in knl_get_dimm_capacity()
1424 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { in knl_get_dimm_capacity()
1428 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1429 pvt->info.dram_rule[sad_rule], &dram_rule); in knl_get_dimm_capacity()
1436 sad_limit = pvt->info.sad_limit(dram_rule)+1; in knl_get_dimm_capacity()
1438 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1439 pvt->info.interleave_list[sad_rule], &interleave_reg); in knl_get_dimm_capacity()
1445 first_pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1448 pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1453 * 0 bit means memory is non-local, in knl_get_dimm_capacity()
1456 edac_dbg(0, "Unexpected interleave target %d\n", in knl_get_dimm_capacity()
1458 return -1; in knl_get_dimm_capacity()
1467 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", in knl_get_dimm_capacity()
1500 tad_size = (tad_limit+1) - in knl_get_dimm_capacity()
1503 tad_base = (tad_limit+1) - tad_size; in knl_get_dimm_capacity()
1507 …edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n… in knl_get_dimm_capacity()
1510 …edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n… in knl_get_dimm_capacity()
1513 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", in knl_get_dimm_capacity()
1532 /* Figure out which channels participate in interleave. */ in knl_get_dimm_capacity()
1573 struct sbridge_pvt *pvt = mci->pvt_info; in get_source_id()
1576 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || in get_source_id()
1577 pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1578 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); in get_source_id()
1580 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); in get_source_id()
1582 if (pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1583 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); in get_source_id()
1585 pvt->sbridge_dev->source_id = SOURCE_ID(reg); in get_source_id()
1590 enum edac_type mode) in __populate_dimms() argument
1592 struct sbridge_pvt *pvt = mci->pvt_info; in __populate_dimms()
1593 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS in __populate_dimms()
1600 mtype = pvt->info.get_memory_type(pvt); in __populate_dimms()
1618 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1620 if (!pvt->knl.pci_channel[i]) in __populate_dimms()
1624 if (!pvt->pci_tad[i]) in __populate_dimms()
1626 pci_read_config_dword(pvt->pci_tad[i], 0x8c, &amap); in __populate_dimms()
1631 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1632 pci_read_config_dword(pvt->knl.pci_channel[i], in __populate_dimms()
1635 pci_read_config_dword(pvt->pci_tad[i], in __populate_dimms()
1641 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { in __populate_dimms()
1643 pvt->sbridge_dev->source_id, in __populate_dimms()
1644 pvt->sbridge_dev->dom, i); in __populate_dimms()
1645 return -ENODEV; in __populate_dimms()
1647 pvt->channel[i].dimms++; in __populate_dimms()
1649 ranks = numrank(pvt->info.type, mtr); in __populate_dimms()
1651 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1661 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); in __populate_dimms()
1665 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, in __populate_dimms()
1669 dimm->nr_pages = npages; in __populate_dimms()
1670 dimm->grain = 32; in __populate_dimms()
1671 dimm->dtype = pvt->info.get_width(pvt, mtr); in __populate_dimms()
1672 dimm->mtype = mtype; in __populate_dimms()
1673 dimm->edac_mode = mode; in __populate_dimms()
1674 pvt->channel[i].dimm[j].rowbits = order_base_2(rows); in __populate_dimms()
1675 pvt->channel[i].dimm[j].colbits = order_base_2(cols); in __populate_dimms()
1676 pvt->channel[i].dimm[j].bank_xor_enable = in __populate_dimms()
1677 GET_BITFIELD(pvt->info.mcmtr, 9, 9); in __populate_dimms()
1678 pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0); in __populate_dimms()
1679 snprintf(dimm->label, sizeof(dimm->label), in __populate_dimms()
1681 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); in __populate_dimms()
1691 struct sbridge_pvt *pvt = mci->pvt_info; in get_dimm_config()
1693 enum edac_type mode; in get_dimm_config() local
1696 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); in get_dimm_config()
1698 pvt->sbridge_dev->mc, in get_dimm_config()
1699 pvt->sbridge_dev->node_id, in get_dimm_config()
1700 pvt->sbridge_dev->source_id); in get_dimm_config()
1705 if (pvt->info.type == KNIGHTS_LANDING) { in get_dimm_config()
1706 mode = EDAC_S4ECD4ED; in get_dimm_config()
1707 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1708 pvt->is_cur_addr_mirrored = false; in get_dimm_config()
1711 return -1; in get_dimm_config()
1712 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1714 return -ENODEV; in get_dimm_config()
1717 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_dimm_config()
1718 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { in get_dimm_config()
1720 return -ENODEV; in get_dimm_config()
1722 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); in get_dimm_config()
1724 pvt->mirror_mode = ADDR_RANGE_MIRRORING; in get_dimm_config()
1729 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { in get_dimm_config()
1731 return -ENODEV; in get_dimm_config()
1734 pvt->mirror_mode = FULL_MIRRORING; in get_dimm_config()
1737 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1742 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1744 return -ENODEV; in get_dimm_config()
1746 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { in get_dimm_config()
1748 mode = EDAC_S8ECD8ED; in get_dimm_config()
1749 pvt->is_lockstep = true; in get_dimm_config()
1752 mode = EDAC_S4ECD4ED; in get_dimm_config()
1753 pvt->is_lockstep = false; in get_dimm_config()
1755 if (IS_CLOSE_PG(pvt->info.mcmtr)) { in get_dimm_config()
1756 edac_dbg(0, "address map is on closed page mode\n"); in get_dimm_config()
1757 pvt->is_close_pg = true; in get_dimm_config()
1759 edac_dbg(0, "address map is on open page mode\n"); in get_dimm_config()
1760 pvt->is_close_pg = false; in get_dimm_config()
1764 return __populate_dimms(mci, knl_mc_sizes, mode); in get_dimm_config()
1769 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_layout()
1781 pvt->tolm = pvt->info.get_tolm(pvt); in get_memory_layout()
1782 tmp_mb = (1 + pvt->tolm) >> 20; in get_memory_layout()
1786 gb, (mb*1000)/1024, (u64)pvt->tolm); in get_memory_layout()
1789 pvt->tohm = pvt->info.get_tohm(pvt); in get_memory_layout()
1790 tmp_mb = (1 + pvt->tohm) >> 20; in get_memory_layout()
1794 gb, (mb*1000)/1024, (u64)pvt->tohm); in get_memory_layout()
1797 * Step 2) Get SAD range and SAD Interleave list in get_memory_layout()
1798 * TAD registers contain the interleave wayness. However, it in get_memory_layout()
1803 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_layout()
1805 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_layout()
1807 limit = pvt->info.sad_limit(reg); in get_memory_layout()
1817 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", in get_memory_layout()
1819 show_dram_attr(pvt->info.dram_attr(reg)), in get_memory_layout()
1822 get_intlv_mode_str(reg, pvt->info.type), in get_memory_layout()
1826 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_layout()
1828 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_layout()
1830 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); in get_memory_layout()
1834 edac_dbg(0, "SAD#%d, interleave #%d: %d\n", in get_memory_layout()
1839 if (pvt->info.type == KNIGHTS_LANDING) in get_memory_layout()
1847 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); in get_memory_layout()
1854 …edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT:… in get_memory_layout()
1871 if (!pvt->channel[i].dimms) in get_memory_layout()
1874 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1891 if (!pvt->channel[i].dimms) in get_memory_layout()
1894 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1901 tmp_mb = pvt->info.rir_limit(reg) >> 20; in get_memory_layout()
1912 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1915 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; in get_memory_layout()
1922 (u32)RIR_RNK_TGT(pvt->info.type, reg), in get_memory_layout()
1934 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) in get_mci_for_node_id()
1935 return sbridge_dev->mci; in get_mci_for_node_id()
1989 pvt = mci->pvt_info; in sb_decode_ddr4()
1990 amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine; in sb_decode_ddr4()
1992 rowbits = pvt->channel[ch].dimm[dimmno].rowbits; in sb_decode_ddr4()
1993 colbits = pvt->channel[ch].dimm[dimmno].colbits; in sb_decode_ddr4()
1994 bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable; in sb_decode_ddr4()
1996 if (pvt->is_lockstep) { in sb_decode_ddr4()
2002 if (pvt->is_close_pg) { in sb_decode_ddr4()
2018 row &= (1u << rowbits) - 1; in sb_decode_ddr4()
2041 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_error_data()
2063 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { in get_memory_error_data()
2065 return -EINVAL; in get_memory_error_data()
2067 if (addr >= (u64)pvt->tohm) { in get_memory_error_data()
2069 return -EINVAL; in get_memory_error_data()
2075 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_error_data()
2076 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_error_data()
2082 limit = pvt->info.sad_limit(reg); in get_memory_error_data()
2085 return -EINVAL; in get_memory_error_data()
2091 if (n_sads == pvt->info.max_sad) { in get_memory_error_data()
2093 return -EINVAL; in get_memory_error_data()
2096 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); in get_memory_error_data()
2097 interleave_mode = pvt->info.interleave_mode(dram_rule); in get_memory_error_data()
2099 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_error_data()
2102 if (pvt->info.type == SANDY_BRIDGE) { in get_memory_error_data()
2103 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_error_data()
2105 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); in get_memory_error_data()
2109 edac_dbg(0, "SAD interleave #%d: %d\n", in get_memory_error_data()
2112 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", in get_memory_error_data()
2113 pvt->sbridge_dev->mc, in get_memory_error_data()
2136 sprintf(msg, "Can't discover socket interleave"); in get_memory_error_data()
2137 return -EINVAL; in get_memory_error_data()
2140 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", in get_memory_error_data()
2142 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_memory_error_data()
2146 /* A7 mode swaps P9 with P6 */ in get_memory_error_data()
2153 /* interleave mode will XOR {8,7,6} with {18,17,16} */ in get_memory_error_data()
2159 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2165 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); in get_memory_error_data()
2169 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", in get_memory_error_data()
2172 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ in get_memory_error_data()
2174 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2177 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", in get_memory_error_data()
2191 return -EINVAL; in get_memory_error_data()
2194 pvt = mci->pvt_info; in get_memory_error_data()
2200 pci_ha = pvt->pci_ha; in get_memory_error_data()
2206 return -EINVAL; in get_memory_error_data()
2214 return -EINVAL; in get_memory_error_data()
2224 if (pvt->is_chan_hash) in get_memory_error_data()
2247 return -EINVAL; in get_memory_error_data()
2251 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); in get_memory_error_data()
2253 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data()
2254 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { in get_memory_error_data()
2263 return -EINVAL; in get_memory_error_data()
2266 pvt->is_cur_addr_mirrored = true; in get_memory_error_data()
2269 pvt->is_cur_addr_mirrored = false; in get_memory_error_data()
2272 if (pvt->is_lockstep) in get_memory_error_data()
2277 …edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (off… in get_memory_error_data()
2294 return -EINVAL; in get_memory_error_data()
2297 ch_addr = addr - offset; in get_memory_error_data()
2301 ch_addr |= addr & ((1 << (6 + shiftup)) - 1); in get_memory_error_data()
2307 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); in get_memory_error_data()
2312 limit = pvt->info.rir_limit(reg); in get_memory_error_data()
2325 return -EINVAL; in get_memory_error_data()
2329 if (pvt->is_close_pg) in get_memory_error_data()
2335 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); in get_memory_error_data()
2336 *rank = RIR_RNK_TGT(pvt->info.type, reg); in get_memory_error_data()
2338 if (pvt->info.type == BROADWELL) { in get_memory_error_data()
2339 if (pvt->is_close_pg) in get_memory_error_data()
2347 rank_addr |= ch_addr & GENMASK_ULL(shiftup - 1, 0); in get_memory_error_data()
2348 rank_addr -= RIR_OFFSET(pvt->info.type, reg); in get_memory_error_data()
2350 mtype = pvt->info.get_memory_type(pvt); in get_memory_error_data()
2360 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", in get_memory_error_data()
2375 u32 reg, channel = GET_BITFIELD(m->status, 0, 3); in get_memory_error_data_from_mce()
2383 return -EINVAL; in get_memory_error_data_from_mce()
2386 pvt = mci->pvt_info; in get_memory_error_data_from_mce()
2387 if (!pvt->info.get_ha) { in get_memory_error_data_from_mce()
2389 return -EINVAL; in get_memory_error_data_from_mce()
2391 *ha = pvt->info.get_ha(m->bank); in get_memory_error_data_from_mce()
2393 sprintf(msg, "Impossible bank %d", m->bank); in get_memory_error_data_from_mce()
2394 return -EINVAL; in get_memory_error_data_from_mce()
2397 *socket = m->socketid; in get_memory_error_data_from_mce()
2401 return -EINVAL; in get_memory_error_data_from_mce()
2404 pvt = new_mci->pvt_info; in get_memory_error_data_from_mce()
2405 pci_ha = pvt->pci_ha; in get_memory_error_data_from_mce()
2407 tad0 = m->addr <= TAD_LIMIT(reg); in get_memory_error_data_from_mce()
2410 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data_from_mce()
2411 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { in get_memory_error_data_from_mce()
2413 pvt->is_cur_addr_mirrored = true; in get_memory_error_data_from_mce()
2415 pvt->is_cur_addr_mirrored = false; in get_memory_error_data_from_mce()
2418 if (pvt->is_lockstep) in get_memory_error_data_from_mce()
2437 for (i = 0; i < sbridge_dev->n_devs; i++) { in sbridge_put_devices()
2438 struct pci_dev *pdev = sbridge_dev->pdev[i]; in sbridge_put_devices()
2442 pdev->bus->number, in sbridge_put_devices()
2443 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); in sbridge_put_devices()
2465 const struct pci_id_descr *dev_descr = &table->descr[devno]; in sbridge_get_onedevice()
2473 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2476 dev_descr->dev_id, *prev); in sbridge_get_onedevice()
2484 if (dev_descr->optional) in sbridge_get_onedevice()
2489 return -ENODEV; in sbridge_get_onedevice()
2493 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2496 return -ENODEV; in sbridge_get_onedevice()
2498 seg = pci_domain_nr(pdev->bus); in sbridge_get_onedevice()
2499 bus = pdev->bus->number; in sbridge_get_onedevice()
2502 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, in sbridge_get_onedevice()
2506 if (dev_descr->dom == IMC1 && devno != 1) { in sbridge_get_onedevice()
2508 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2513 if (dev_descr->dom == SOCK) in sbridge_get_onedevice()
2516 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); in sbridge_get_onedevice()
2519 return -ENOMEM; in sbridge_get_onedevice()
2524 if (sbridge_dev->pdev[sbridge_dev->i_devs]) { in sbridge_get_onedevice()
2527 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2529 return -ENODEV; in sbridge_get_onedevice()
2532 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; in sbridge_get_onedevice()
2538 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) in sbridge_get_onedevice()
2546 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2547 return -ENODEV; in sbridge_get_onedevice()
2551 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2566 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2582 if (table->type == KNIGHTS_LANDING) in sbridge_get_all_devices()
2584 while (table && table->descr) { in sbridge_get_all_devices()
2585 for (i = 0; i < table->n_devs_per_sock; i++) { in sbridge_get_all_devices()
2587 table->descr[i].dev_id != in sbridge_get_all_devices()
2588 table->descr[i-1].dev_id) { in sbridge_get_all_devices()
2596 i = table->n_devs_per_sock; in sbridge_get_all_devices()
2600 return -ENODEV; in sbridge_get_all_devices()
2615 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2620 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mci_bind_devs()
2625 for (i = 0; i < sbridge_dev->n_devs; i++) { in sbridge_mci_bind_devs()
2626 pdev = sbridge_dev->pdev[i]; in sbridge_mci_bind_devs()
2630 switch (pdev->device) { in sbridge_mci_bind_devs()
2632 pvt->pci_sad0 = pdev; in sbridge_mci_bind_devs()
2635 pvt->pci_sad1 = pdev; in sbridge_mci_bind_devs()
2638 pvt->pci_br0 = pdev; in sbridge_mci_bind_devs()
2641 pvt->pci_ha = pdev; in sbridge_mci_bind_devs()
2644 pvt->pci_ta = pdev; in sbridge_mci_bind_devs()
2647 pvt->pci_ras = pdev; in sbridge_mci_bind_devs()
2654 int id = TAD_DEV_TO_CHAN(pdev->device); in sbridge_mci_bind_devs()
2655 pvt->pci_tad[id] = pdev; in sbridge_mci_bind_devs()
2660 pvt->pci_ddrio = pdev; in sbridge_mci_bind_devs()
2667 pdev->vendor, pdev->device, in sbridge_mci_bind_devs()
2668 sbridge_dev->bus, in sbridge_mci_bind_devs()
2673 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || in sbridge_mci_bind_devs()
2674 !pvt->pci_ras || !pvt->pci_ta) in sbridge_mci_bind_devs()
2683 return -ENODEV; in sbridge_mci_bind_devs()
2687 PCI_VENDOR_ID_INTEL, pdev->device); in sbridge_mci_bind_devs()
2688 return -EINVAL; in sbridge_mci_bind_devs()
2694 struct sbridge_pvt *pvt = mci->pvt_info; in ibridge_mci_bind_devs()
2699 for (i = 0; i < sbridge_dev->n_devs; i++) { in ibridge_mci_bind_devs()
2700 pdev = sbridge_dev->pdev[i]; in ibridge_mci_bind_devs()
2704 switch (pdev->device) { in ibridge_mci_bind_devs()
2707 pvt->pci_ha = pdev; in ibridge_mci_bind_devs()
2711 pvt->pci_ta = pdev; in ibridge_mci_bind_devs()
2715 pvt->pci_ras = pdev; in ibridge_mci_bind_devs()
2726 int id = TAD_DEV_TO_CHAN(pdev->device); in ibridge_mci_bind_devs()
2727 pvt->pci_tad[id] = pdev; in ibridge_mci_bind_devs()
2732 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2735 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2738 pvt->pci_sad0 = pdev; in ibridge_mci_bind_devs()
2741 pvt->pci_br0 = pdev; in ibridge_mci_bind_devs()
2744 pvt->pci_br1 = pdev; in ibridge_mci_bind_devs()
2751 sbridge_dev->bus, in ibridge_mci_bind_devs()
2752 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in ibridge_mci_bind_devs()
2757 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || in ibridge_mci_bind_devs()
2758 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) in ibridge_mci_bind_devs()
2761 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in ibridge_mci_bind_devs()
2762 saw_chan_mask != 0x03) /* -EP */ in ibridge_mci_bind_devs()
2768 return -ENODEV; in ibridge_mci_bind_devs()
2773 pdev->device); in ibridge_mci_bind_devs()
2774 return -EINVAL; in ibridge_mci_bind_devs()
2780 struct sbridge_pvt *pvt = mci->pvt_info; in haswell_mci_bind_devs()
2786 if (pvt->info.pci_vtd == NULL) in haswell_mci_bind_devs()
2788 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in haswell_mci_bind_devs()
2792 for (i = 0; i < sbridge_dev->n_devs; i++) { in haswell_mci_bind_devs()
2793 pdev = sbridge_dev->pdev[i]; in haswell_mci_bind_devs()
2797 switch (pdev->device) { in haswell_mci_bind_devs()
2799 pvt->pci_sad0 = pdev; in haswell_mci_bind_devs()
2802 pvt->pci_sad1 = pdev; in haswell_mci_bind_devs()
2806 pvt->pci_ha = pdev; in haswell_mci_bind_devs()
2810 pvt->pci_ta = pdev; in haswell_mci_bind_devs()
2814 pvt->pci_ras = pdev; in haswell_mci_bind_devs()
2825 int id = TAD_DEV_TO_CHAN(pdev->device); in haswell_mci_bind_devs()
2826 pvt->pci_tad[id] = pdev; in haswell_mci_bind_devs()
2834 if (!pvt->pci_ddrio) in haswell_mci_bind_devs()
2835 pvt->pci_ddrio = pdev; in haswell_mci_bind_devs()
2842 sbridge_dev->bus, in haswell_mci_bind_devs()
2843 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in haswell_mci_bind_devs()
2848 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in haswell_mci_bind_devs()
2849 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in haswell_mci_bind_devs()
2852 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in haswell_mci_bind_devs()
2853 saw_chan_mask != 0x03) /* -EP */ in haswell_mci_bind_devs()
2859 return -ENODEV; in haswell_mci_bind_devs()
2865 struct sbridge_pvt *pvt = mci->pvt_info; in broadwell_mci_bind_devs()
2871 if (pvt->info.pci_vtd == NULL) in broadwell_mci_bind_devs()
2873 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in broadwell_mci_bind_devs()
2877 for (i = 0; i < sbridge_dev->n_devs; i++) { in broadwell_mci_bind_devs()
2878 pdev = sbridge_dev->pdev[i]; in broadwell_mci_bind_devs()
2882 switch (pdev->device) { in broadwell_mci_bind_devs()
2884 pvt->pci_sad0 = pdev; in broadwell_mci_bind_devs()
2887 pvt->pci_sad1 = pdev; in broadwell_mci_bind_devs()
2891 pvt->pci_ha = pdev; in broadwell_mci_bind_devs()
2895 pvt->pci_ta = pdev; in broadwell_mci_bind_devs()
2899 pvt->pci_ras = pdev; in broadwell_mci_bind_devs()
2910 int id = TAD_DEV_TO_CHAN(pdev->device); in broadwell_mci_bind_devs()
2911 pvt->pci_tad[id] = pdev; in broadwell_mci_bind_devs()
2916 pvt->pci_ddrio = pdev; in broadwell_mci_bind_devs()
2923 sbridge_dev->bus, in broadwell_mci_bind_devs()
2924 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in broadwell_mci_bind_devs()
2929 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in broadwell_mci_bind_devs()
2930 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in broadwell_mci_bind_devs()
2933 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in broadwell_mci_bind_devs()
2934 saw_chan_mask != 0x03) /* -EP */ in broadwell_mci_bind_devs()
2940 return -ENODEV; in broadwell_mci_bind_devs()
2946 struct sbridge_pvt *pvt = mci->pvt_info; in knl_mci_bind_devs()
2953 for (i = 0; i < sbridge_dev->n_devs; i++) { in knl_mci_bind_devs()
2954 pdev = sbridge_dev->pdev[i]; in knl_mci_bind_devs()
2959 dev = (pdev->devfn >> 3) & 0x1f; in knl_mci_bind_devs()
2960 func = pdev->devfn & 0x7; in knl_mci_bind_devs()
2962 switch (pdev->device) { in knl_mci_bind_devs()
2965 pvt->knl.pci_mc0 = pdev; in knl_mci_bind_devs()
2967 pvt->knl.pci_mc1 = pdev; in knl_mci_bind_devs()
2977 pvt->pci_sad0 = pdev; in knl_mci_bind_devs()
2981 pvt->pci_sad1 = pdev; in knl_mci_bind_devs()
2988 devidx = ((dev-14)*8)+func; in knl_mci_bind_devs()
2997 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); in knl_mci_bind_devs()
2999 pvt->knl.pci_cha[devidx] = pdev; in knl_mci_bind_devs()
3003 devidx = -1; in knl_mci_bind_devs()
3006 * MC0 channels 0-2 are device 9 function 2-4, in knl_mci_bind_devs()
3007 * MC1 channels 3-5 are device 8 function 2-4. in knl_mci_bind_devs()
3011 devidx = func-2; in knl_mci_bind_devs()
3013 devidx = 3 + (func-2); in knl_mci_bind_devs()
3022 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); in knl_mci_bind_devs()
3023 pvt->knl.pci_channel[devidx] = pdev; in knl_mci_bind_devs()
3027 pvt->knl.pci_mc_info = pdev; in knl_mci_bind_devs()
3031 pvt->pci_ta = pdev; in knl_mci_bind_devs()
3036 pdev->device); in knl_mci_bind_devs()
3041 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || in knl_mci_bind_devs()
3042 !pvt->pci_sad0 || !pvt->pci_sad1 || in knl_mci_bind_devs()
3043 !pvt->pci_ta) { in knl_mci_bind_devs()
3048 if (!pvt->knl.pci_channel[i]) { in knl_mci_bind_devs()
3055 if (!pvt->knl.pci_cha[i]) { in knl_mci_bind_devs()
3065 return -ENODEV; in knl_mci_bind_devs()
3082 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mce_output_error()
3084 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); in sbridge_mce_output_error()
3085 bool overflow = GET_BITFIELD(m->status, 62, 62); in sbridge_mce_output_error()
3086 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); in sbridge_mce_output_error()
3088 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); in sbridge_mce_output_error()
3089 u32 mscod = GET_BITFIELD(m->status, 16, 31); in sbridge_mce_output_error()
3090 u32 errcode = GET_BITFIELD(m->status, 0, 15); in sbridge_mce_output_error()
3091 u32 channel = GET_BITFIELD(m->status, 0, 3); in sbridge_mce_output_error()
3092 u32 optypenum = GET_BITFIELD(m->status, 4, 6); in sbridge_mce_output_error()
3094 * Bits 5-0 of MCi_MISC give the least significant bit that is valid. in sbridge_mce_output_error()
3098 u32 lsb = GET_BITFIELD(m->misc, 0, 5); in sbridge_mce_output_error()
3104 if (pvt->info.type != SANDY_BRIDGE) in sbridge_mce_output_error()
3107 recoverable = GET_BITFIELD(m->status, 56, 56); in sbridge_mce_output_error()
3121 * According with Table 15-9 of the Intel Architecture spec vol 3A, in sbridge_mce_output_error()
3152 if (pvt->info.type == KNIGHTS_LANDING) { in sbridge_mce_output_error()
3159 m->bank); in sbridge_mce_output_error()
3164 * Reported channel is in range 0-2, so we can't map it in sbridge_mce_output_error()
3169 channel = knl_channel_remap(m->bank == 16, channel); in sbridge_mce_output_error()
3179 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, in sbridge_mce_output_error()
3180 channel, 0, -1, in sbridge_mce_output_error()
3185 rc = get_memory_error_data(mci, m->addr, &socket, &ha, in sbridge_mce_output_error()
3201 pvt = mci->pvt_info; in sbridge_mce_output_error()
3206 dimm = -1; in sbridge_mce_output_error()
3220 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) in sbridge_mce_output_error()
3237 channel = -1; in sbridge_mce_output_error()
3241 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, in sbridge_mce_output_error()
3242 channel, dimm, -1, in sbridge_mce_output_error()
3247 -1, -1, -1, in sbridge_mce_output_error()
3263 if (mce->kflags & MCE_HANDLED_CEC) in sbridge_mce_check_error()
3269 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. in sbridge_mce_check_error()
3272 if ((mce->status & 0xefff) >> 7 != 1) in sbridge_mce_check_error()
3276 if (!GET_BITFIELD(mce->status, 58, 58)) in sbridge_mce_check_error()
3280 if (!GET_BITFIELD(mce->status, 59, 59)) in sbridge_mce_check_error()
3284 if (GET_BITFIELD(mce->misc, 6, 8) != 2) in sbridge_mce_check_error()
3287 mci = get_mci_for_node_id(mce->socketid, IMC0); in sbridge_mce_check_error()
3291 if (mce->mcgstatus & MCG_STATUS_MCIP) in sbridge_mce_check_error()
3299 "Bank %d: %016Lx\n", mce->extcpu, type, in sbridge_mce_check_error()
3300 mce->mcgstatus, mce->bank, mce->status); in sbridge_mce_check_error()
3301 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); in sbridge_mce_check_error()
3302 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); in sbridge_mce_check_error()
3303 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); in sbridge_mce_check_error()
3306 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, in sbridge_mce_check_error()
3307 mce->time, mce->socketid, mce->apicid); in sbridge_mce_check_error()
3312 mce->kflags |= MCE_HANDLED_EDAC; in sbridge_mce_check_error()
3327 struct mem_ctl_info *mci = sbridge_dev->mci; in sbridge_unregister_mci()
3329 if (unlikely(!mci || !mci->pvt_info)) { in sbridge_unregister_mci()
3330 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); in sbridge_unregister_mci()
3337 mci, &sbridge_dev->pdev[0]->dev); in sbridge_unregister_mci()
3340 edac_mc_del_mc(mci->pdev); in sbridge_unregister_mci()
3342 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); in sbridge_unregister_mci()
3343 kfree(mci->ctl_name); in sbridge_unregister_mci()
3345 sbridge_dev->mci = NULL; in sbridge_unregister_mci()
3353 struct pci_dev *pdev = sbridge_dev->pdev[0]; in sbridge_register_mci()
3364 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, in sbridge_register_mci()
3368 return -ENOMEM; in sbridge_register_mci()
3371 mci, &pdev->dev); in sbridge_register_mci()
3373 pvt = mci->pvt_info; in sbridge_register_mci()
3377 pvt->sbridge_dev = sbridge_dev; in sbridge_register_mci()
3378 sbridge_dev->mci = mci; in sbridge_register_mci()
3380 mci->mtype_cap = type == KNIGHTS_LANDING ? in sbridge_register_mci()
3382 mci->edac_ctl_cap = EDAC_FLAG_NONE; in sbridge_register_mci()
3383 mci->edac_cap = EDAC_FLAG_NONE; in sbridge_register_mci()
3384 mci->mod_name = EDAC_MOD_STR; in sbridge_register_mci()
3385 mci->dev_name = pci_name(pdev); in sbridge_register_mci()
3386 mci->ctl_page_to_phys = NULL; in sbridge_register_mci()
3388 pvt->info.type = type; in sbridge_register_mci()
3391 pvt->info.rankcfgr = IB_RANK_CFG_A; in sbridge_register_mci()
3392 pvt->info.get_tolm = ibridge_get_tolm; in sbridge_register_mci()
3393 pvt->info.get_tohm = ibridge_get_tohm; in sbridge_register_mci()
3394 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3395 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3396 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3397 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3398 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3399 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3400 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3401 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3402 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3403 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3404 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3405 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3412 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", in sbridge_register_mci()
3413 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3416 pvt->info.rankcfgr = SB_RANK_CFG_A; in sbridge_register_mci()
3417 pvt->info.get_tolm = sbridge_get_tolm; in sbridge_register_mci()
3418 pvt->info.get_tohm = sbridge_get_tohm; in sbridge_register_mci()
3419 pvt->info.dram_rule = sbridge_dram_rule; in sbridge_register_mci()
3420 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3421 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3422 pvt->info.get_ha = sbridge_get_ha; in sbridge_register_mci()
3423 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3424 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3425 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3426 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3427 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); in sbridge_register_mci()
3428 pvt->info.interleave_list = sbridge_interleave_list; in sbridge_register_mci()
3429 pvt->info.interleave_pkg = sbridge_interleave_pkg; in sbridge_register_mci()
3430 pvt->info.get_width = sbridge_get_width; in sbridge_register_mci()
3437 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", in sbridge_register_mci()
3438 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3442 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3443 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3444 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3445 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3446 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3447 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3448 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3449 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3450 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3451 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3452 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3453 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3454 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3455 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3462 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", in sbridge_register_mci()
3463 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3467 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3468 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3469 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3470 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3471 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3472 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3473 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3474 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3475 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3476 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3477 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3478 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3479 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3480 pvt->info.get_width = broadwell_get_width; in sbridge_register_mci()
3487 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", in sbridge_register_mci()
3488 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3491 /* pvt->info.rankcfgr == ??? */ in sbridge_register_mci()
3492 pvt->info.get_tolm = knl_get_tolm; in sbridge_register_mci()
3493 pvt->info.get_tohm = knl_get_tohm; in sbridge_register_mci()
3494 pvt->info.dram_rule = knl_dram_rule; in sbridge_register_mci()
3495 pvt->info.get_memory_type = knl_get_memory_type; in sbridge_register_mci()
3496 pvt->info.get_node_id = knl_get_node_id; in sbridge_register_mci()
3497 pvt->info.get_ha = knl_get_ha; in sbridge_register_mci()
3498 pvt->info.rir_limit = NULL; in sbridge_register_mci()
3499 pvt->info.sad_limit = knl_sad_limit; in sbridge_register_mci()
3500 pvt->info.interleave_mode = knl_interleave_mode; in sbridge_register_mci()
3501 pvt->info.dram_attr = dram_attr_knl; in sbridge_register_mci()
3502 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); in sbridge_register_mci()
3503 pvt->info.interleave_list = knl_interleave_list; in sbridge_register_mci()
3504 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3505 pvt->info.get_width = knl_get_width; in sbridge_register_mci()
3511 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", in sbridge_register_mci()
3512 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3516 if (!mci->ctl_name) { in sbridge_register_mci()
3517 rc = -ENOMEM; in sbridge_register_mci()
3530 mci->pdev = &pdev->dev; in sbridge_register_mci()
3535 rc = -EINVAL; in sbridge_register_mci()
3542 kfree(mci->ctl_name); in sbridge_register_mci()
3545 sbridge_dev->mci = NULL; in sbridge_register_mci()
3574 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; in sbridge_probe()
3590 sbridge_dev->mc = mc++; in sbridge_probe()
3591 rc = sbridge_register_mci(sbridge_dev, ptable->type); in sbridge_probe()
3639 return -EBUSY; in sbridge_init()
3643 return -EBUSY; in sbridge_init()
3646 return -ENODEV; in sbridge_init()
3650 return -ENODEV; in sbridge_init()
3688 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "