drivers/edac/ie31200_edac.c

3  * Intel E3-1200
6  * Support for the E3-1200 processor family. Heavily based on previous
14  * 0108: Xeon E3-1200 Processor Family DRAM Controller
15  * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16  * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17  * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18  * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21  * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
22  * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
25  * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
28 …* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-dat…
29  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
31 …* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-dat…
43  * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
245 	pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);  in ecc_capable()
389 	dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;  in __populate_dimm_info()
445 	edac_dbg(3, "MC: init mci\n");  in ie31200_probe1()
529 		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");  in ie31200_probe1()
535 	edac_dbg(3, "MC: success\n");  in ie31200_probe1()
615 	edac_dbg(3, "MC:\n");  in ie31200_init()
656 	edac_dbg(3, "MC:\n");  in ie31200_exit()