19  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1  0x0108
61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2  0x010c
62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3  0x0150
63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4  0x0158
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5  0x015c
65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6  0x0c04
66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7  0x0c08
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8  0x190F
68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9  0x1918
69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1    0x3e0f
75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2    0x3e18
76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3    0x3e1f
77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4    0x3e30
78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5    0x3e31
79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6    0x3e32
80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7    0x3e33
81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8    0x3ec2
82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9    0x3ec6
83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10   0x3eca
100 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
101 #define IE31200_MCHBAR_LOW		0x48
102 #define IE31200_MCHBAR_HIGH		0x4c
123  *  0    Single-bit DRAM ECC Error Flag (DSERR)
125 #define IE31200_ERRSTS			0xc8
127 #define IE31200_ERRSTS_CE		BIT(0)
131  * Channel 0 ECC Error Log (64b)
141  *    0  Correctable Error Status (CERRSTS)
144 #define IE31200_C0ECCERRLOG			0x40c8
145 #define IE31200_C1ECCERRLOG			0x44c8
146 #define IE31200_C0ECCERRLOG_SKL			0x4048
147 #define IE31200_C1ECCERRLOG_SKL			0x4448
148 #define IE31200_ECCERRLOG_CE			BIT(0)
159 #define IE31200_CAPID0			0xe4
164 #define IE31200_MAD_DIMM_0_OFFSET		0x5004
165 #define IE31200_MAD_DIMM_0_OFFSET_SKL		0x500C
166 #define IE31200_MAD_DIMM_SIZE			GENMASK_ULL(7, 0)
191 	IE31200 = 0,
213 	   x16_width : 2; /* 0 means x8 width */
225 		edac_dbg(0, "In single channel mode\n");  in how_many_channels()
228 		edac_dbg(0, "In dual channel mode\n");  in how_many_channels()
234 		edac_dbg(0, "2 DIMMS per channel disabled\n");  in how_many_channels()
236 		edac_dbg(0, "2 DIMMS per channel enabled\n");  in how_many_channels()
284 	info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
297 		info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
316 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,  in ie31200_process_error_info()
321 	for (channel = 0; channel < nr_channels; channel++) {  in ie31200_process_error_info()
325 					     0, 0, 0,  in ie31200_process_error_info()
331 					     0, 0,  in ie31200_process_error_info()
364 		ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",  in ie31200_map_mchbar()
371 		ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",  in ie31200_map_mchbar()
381 	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;  in __skl_populate_dimm_info()
390 	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;  in __populate_dimm_info()
391 	dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;  in __populate_dimm_info()
420 	edac_dbg(0, "MC:\n");  in ie31200_probe1()
428 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in ie31200_probe1()
429 	layers[0].size = IE31200_DIMMS;  in ie31200_probe1()
430 	layers[0].is_virt_csrow = true;  in ie31200_probe1()
434 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,  in ie31200_probe1()
471 	for (i = 0; i < IE31200_CHANNELS; i++) {  in ie31200_probe1()
474 		edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);  in ie31200_probe1()
475 		for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {  in ie31200_probe1()
478 			edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",  in ie31200_probe1()
491 	for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {  in ie31200_probe1()
492 		for (j = 0; j < IE31200_CHANNELS; j++) {  in ie31200_probe1()
497 			if (nr_pages == 0)  in ie31200_probe1()
502 				dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);  in ie31200_probe1()
504 				edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);  in ie31200_probe1()
513 			dimm = edac_get_dimm(mci, i * 2, j, 0);  in ie31200_probe1()
515 			edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);  in ie31200_probe1()
536 	return 0;  in ie31200_probe1()
552 	edac_dbg(0, "MC:\n");  in ie31200_init_one()
553 	if (pci_enable_device(pdev) < 0)  in ie31200_init_one()
556 	if (rc == 0 && !mci_pdev)  in ie31200_init_one()
567 	edac_dbg(0, "\n");  in ie31200_remove_one()
579 	{ PCI_VEND_DEV(INTEL, IE31200_HB_1),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
580 	{ PCI_VEND_DEV(INTEL, IE31200_HB_2),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
581 	{ PCI_VEND_DEV(INTEL, IE31200_HB_3),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
582 	{ PCI_VEND_DEV(INTEL, IE31200_HB_4),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
583 	{ PCI_VEND_DEV(INTEL, IE31200_HB_5),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
584 	{ PCI_VEND_DEV(INTEL, IE31200_HB_6),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
585 	{ PCI_VEND_DEV(INTEL, IE31200_HB_7),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
586 	{ PCI_VEND_DEV(INTEL, IE31200_HB_8),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
587 	{ PCI_VEND_DEV(INTEL, IE31200_HB_9),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
588 	{ PCI_VEND_DEV(INTEL, IE31200_HB_10),     PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
589 	{ PCI_VEND_DEV(INTEL, IE31200_HB_11),     PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
590 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
591 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
592 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
593 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
594 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
595 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
596 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
597 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
598 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
599 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
600 	{ 0, } /* 0 terminated list. */
620 	if (pci_rc < 0)  in ie31200_init()
624 		ie31200_registered = 0;  in ie31200_init()
625 		for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {  in ie31200_init()
633 			edac_dbg(0, "ie31200 pci_get_device fail\n");  in ie31200_init()
638 		if (pci_rc < 0) {  in ie31200_init()
639 			edac_dbg(0, "ie31200 init fail\n");  in ie31200_init()
644 	return 0;  in ie31200_init()