8  * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
20  * not completely so - I haven't studied them in enough detail to know
25 #include <linux/init.h>
38  * rows" "The 82443BX supports multiple-bit error detection and
39  * single-bit error correction when ECC mode is enabled and
40  * single/multi-bit error detection when correction is disabled.
42  * on a QWord basis. Partial QWord writes require a read-modify-write
48  * error within the same QWord would result in a double-bit error
50  * it requires no software intervention to correct the data in memory."
65 						 * row is non-ECC */
69 #define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0	/* 00 = Non-ECC */
81 #define I82443BXGX_EAP_OFFSET_MBE  BIT(1)	/* Err at EAP was multi-bit (W1TC) */
82 #define I82443BXGX_EAP_OFFSET_SBE  BIT(0)	/* Err at EAP was single-bit (W1TC) */
91 #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5	/* 3 bits - first err row multibit */
93 #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1	/* 3 bits - first err row singlebit */
106 /* FIXME - don't poll when ECC disabled? */
114 static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
125 	pdev = to_pci_dev(mci->pdev);  in i82443bxgx_edacmc_get_error_info()
126 	pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);  in i82443bxgx_edacmc_get_error_info()
127 	if (info->eap & I82443BXGX_EAP_OFFSET_SBE)  in i82443bxgx_edacmc_get_error_info()
133 	if (info->eap & I82443BXGX_EAP_OFFSET_MBE)  in i82443bxgx_edacmc_get_error_info()
150 	eapaddr = (info->eap & 0xfffff000);  in i82443bxgx_edacmc_process_error_info()
152 	pageoffset = eapaddr - (page << PAGE_SHIFT);  in i82443bxgx_edacmc_process_error_info()
154 	if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {  in i82443bxgx_edacmc_process_error_info()
160 					     0, -1, mci->ctl_name, "");  in i82443bxgx_edacmc_process_error_info()
163 	if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {  in i82443bxgx_edacmc_process_error_info()
169 					     0, -1, mci->ctl_name, "");  in i82443bxgx_edacmc_process_error_info()
196 	for (index = 0; index < mci->nr_csrows; index++) {  in i82443bxgx_init_csrows()
197 		csrow = mci->csrows[index];  in i82443bxgx_init_csrows()
198 		dimm = csrow->channels[0]->dimm;  in i82443bxgx_init_csrows()
202 			 mci->mc_idx, index, drbar);  in i82443bxgx_init_csrows()
206 			 mci->mc_idx, index, row_high_limit,  in i82443bxgx_init_csrows()
217 		csrow->first_page = row_base >> PAGE_SHIFT;  in i82443bxgx_init_csrows()
218 		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;  in i82443bxgx_init_csrows()
219 		dimm->nr_pages = csrow->last_page - csrow->first_page + 1;  in i82443bxgx_init_csrows()
221 		dimm->grain = 1 << 12;  in i82443bxgx_init_csrows()
222 		dimm->mtype = mtype;  in i82443bxgx_init_csrows()
224 		dimm->dtype = DEV_UNKNOWN;  in i82443bxgx_init_csrows()
225 		/* Mode is global to all rows on 440BX */  in i82443bxgx_init_csrows()
226 		dimm->edac_mode = edac_mode;  in i82443bxgx_init_csrows()
246 		return -EIO;  in i82443bxgx_edacmc_probe1()
256 		return -ENOMEM;  in i82443bxgx_edacmc_probe1()
259 	mci->pdev = &pdev->dev;  in i82443bxgx_edacmc_probe1()
260 	mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;  in i82443bxgx_edacmc_probe1()
261 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;  in i82443bxgx_edacmc_probe1()
275 		mtype = -MEM_UNKNOWN;  in i82443bxgx_edacmc_probe1()
279 		mci->edac_cap = mci->edac_ctl_cap;  in i82443bxgx_edacmc_probe1()
281 		mci->edac_cap = EDAC_FLAG_NONE;  in i82443bxgx_edacmc_probe1()
283 	mci->scrub_cap = SCRUB_FLAG_HW_SRC;  in i82443bxgx_edacmc_probe1()
288 	mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)  in i82443bxgx_edacmc_probe1()
310 	/* Many BIOSes don't clear error flags on boot, so do this  in i82443bxgx_edacmc_probe1()
311 	 * here, or we get "phantom" errors occurring at module-load  in i82443bxgx_edacmc_probe1()
319 	mci->mod_name = EDAC_MOD_STR;  in i82443bxgx_edacmc_probe1()
320 	mci->ctl_name = "I82443BXGX";  in i82443bxgx_edacmc_probe1()
321 	mci->dev_name = pci_name(pdev);  in i82443bxgx_edacmc_probe1()
322 	mci->edac_check = i82443bxgx_edacmc_check;  in i82443bxgx_edacmc_probe1()
323 	mci->ctl_page_to_phys = NULL;  in i82443bxgx_edacmc_probe1()
331 	i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);  in i82443bxgx_edacmc_probe1()
346 	return -ENODEV;  in i82443bxgx_edacmc_probe1()
349 /* returns count (>= 0), or negative on error */
358 	rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);  in i82443bxgx_edacmc_init_one()
375 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)  in i82443bxgx_edacmc_remove_one()
401        /* Ensure that the OPSTATE is set correctly for POLL or NMI */  in i82443bxgx_edacmc_init()
413 		while (mci_pdev == NULL && id->vendor != 0) {  in i82443bxgx_edacmc_init()
414 			mci_pdev = pci_get_device(id->vendor,  in i82443bxgx_edacmc_init()
415 					id->device, NULL);  in i82443bxgx_edacmc_init()
421 			pci_rc = -ENODEV;  in i82443bxgx_edacmc_init()
428 			edac_dbg(0, "i82443bxgx init fail\n");  in i82443bxgx_edacmc_init()
429 			pci_rc = -ENODEV;  in i82443bxgx_edacmc_init()
458 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
462 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");