286 #define MTR_DIMMS_PRESENT(mtr)		((mtr) & (1 << 10))  argument
287 #define MTR_DIMMS_ETHROTTLE(mtr)	((mtr) & (1 << 9))  argument
288 #define MTR_DRAM_WIDTH(mtr)		(((mtr) & (1 << 8)) ? 8 : 4)  argument
289 #define MTR_DRAM_BANKS(mtr)		(((mtr) & (1 << 6)) ? 8 : 4)  argument
290 #define MTR_DRAM_BANKS_ADDR_BITS(mtr)	((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)  argument
291 #define MTR_DIMM_RANK(mtr)		(((mtr) >> 5) & 0x1)  argument
292 #define MTR_DIMM_RANK_ADDR_BITS(mtr)	(MTR_DIMM_RANK(mtr) ? 2 : 1)  argument
293 #define MTR_DIMM_ROWS(mtr)		(((mtr) >> 2) & 0x3)  argument
294 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)	(MTR_DIMM_ROWS(mtr) + 13)  argument
295 #define MTR_DIMM_COLS(mtr)		((mtr) & 0x3)  argument
296 #define MTR_DIMM_COLS_ADDR_BITS(mtr)	(MTR_DIMM_COLS(mtr) + 10)  argument
864 	int mtr;  in determine_mtr()  local
879 		mtr = pvt->b0_mtr[n];  in determine_mtr()
881 		mtr = pvt->b1_mtr[n];  in determine_mtr()
883 	return mtr;  in determine_mtr()
888 static void decode_mtr(int slot_row, u16 mtr)  in decode_mtr()  argument
892 	ans = MTR_DIMMS_PRESENT(mtr);  in decode_mtr()
895 		 slot_row, mtr, ans ? "" : "NOT ");  in decode_mtr()
899 	edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));  in decode_mtr()
902 		 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");  in decode_mtr()
904 	edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));  in decode_mtr()
906 		 MTR_DIMM_RANK(mtr) ? "double" : "single");  in decode_mtr()
908 		 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :  in decode_mtr()
909 		 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :  in decode_mtr()
910 		 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :  in decode_mtr()
913 		 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :  in decode_mtr()
914 		 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :  in decode_mtr()
915 		 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :  in decode_mtr()
922 	int mtr;  in handle_channel()  local
926 	mtr = determine_mtr(pvt, dimm, channel);  in handle_channel()
927 	if (MTR_DIMMS_PRESENT(mtr)) {  in handle_channel()
934 			addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);  in handle_channel()
936 			addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);  in handle_channel()
938 			addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);  in handle_channel()
940 			addrBits += MTR_DIMM_RANK(mtr);  in handle_channel()
1170 	int mtr;  in i5400_init_dimms()  local
1185 			mtr = determine_mtr(pvt, slot, channel);  in i5400_init_dimms()
1188 			if (!MTR_DIMMS_PRESENT(mtr))  in i5400_init_dimms()
1201 			dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ?  in i5400_init_dimms()
1208 			dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ?  in i5400_init_dimms()