Lines Matching refs:res_cfg
27 (res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg))
30 (res_cfg->type == GNR ? 12 : 8), &(reg))
35 res_cfg->type == GNR ? 0x290 : 0x90, &(reg))
38 res_cfg->type == GNR ? 0x298 : 0x98, &(reg))
41 (res_cfg->type == GNR ? 0xc0c : 0x2080c)) + \
48 (res_cfg->type == GNR ? 0xaf8 : 0x20ef8)) + \
83 static struct res_config *res_cfg; variable
166 imc_num = res_cfg->ddr_imc_num; in enable_retry_rd_err_log()
167 chan_num = res_cfg->ddr_chan_num; in enable_retry_rd_err_log()
176 res_cfg->offsets_scrub, in enable_retry_rd_err_log()
177 res_cfg->offsets_demand, in enable_retry_rd_err_log()
178 res_cfg->offsets_demand2); in enable_retry_rd_err_log()
181 imc_num += res_cfg->hbm_imc_num; in enable_retry_rd_err_log()
182 chan_num = res_cfg->hbm_chan_num; in enable_retry_rd_err_log()
191 res_cfg->offsets_scrub_hbm0, in enable_retry_rd_err_log()
192 res_cfg->offsets_demand_hbm0, in enable_retry_rd_err_log()
195 res_cfg->offsets_scrub_hbm1, in enable_retry_rd_err_log()
196 res_cfg->offsets_demand_hbm1, in enable_retry_rd_err_log()
223 offsets = scrub_err ? res_cfg->offsets_scrub_hbm1 : in show_retry_rd_err_log()
224 res_cfg->offsets_demand_hbm1; in show_retry_rd_err_log()
226 offsets = scrub_err ? res_cfg->offsets_scrub_hbm0 : in show_retry_rd_err_log()
227 res_cfg->offsets_demand_hbm0; in show_retry_rd_err_log()
230 offsets = res_cfg->offsets_scrub; in show_retry_rd_err_log()
232 offsets = res_cfg->offsets_demand; in show_retry_rd_err_log()
233 xffsets = res_cfg->offsets_demand2; in show_retry_rd_err_log()
251 if (res_cfg->type == SPR) { in show_retry_rd_err_log()
353 d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->pcu_cr3_bdf.bus], in i10nm_get_imc_num()
354 res_cfg->pcu_cr3_bdf.dev, in i10nm_get_imc_num()
355 res_cfg->pcu_cr3_bdf.fun); in i10nm_get_imc_num()
414 d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->sad_all_bdf.bus], in i10nm_check_2lm()
415 res_cfg->sad_all_bdf.dev, in i10nm_check_2lm()
416 res_cfg->sad_all_bdf.fun); in i10nm_check_2lm()
438 switch (res_cfg->type) { in i10nm_mscod_is_ddrt()
485 switch (res_cfg->type) { in i10nm_mc_decode_available()
526 switch (res_cfg->type) { in i10nm_mc_decode()
586 d->bus[res_cfg->ddr_mdev_bdf.bus], in get_gnr_mdev()
587 res_cfg->ddr_mdev_bdf.dev + i / 7, in get_gnr_mdev()
588 res_cfg->ddr_mdev_bdf.fun + i % 7); in get_gnr_mdev()
620 switch (res_cfg->type) { in get_ddr_munit()
644 d->bus[res_cfg->ddr_mdev_bdf.bus], in get_ddr_munit()
645 res_cfg->ddr_mdev_bdf.dev + i, in get_ddr_munit()
646 res_cfg->ddr_mdev_bdf.fun); in get_ddr_munit()
669 switch (res_cfg->type) { in i10nm_imc_absent()
671 for (i = 0; i < res_cfg->ddr_chan_num; i++) { in i10nm_imc_absent()
704 d->util_all = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->util_all_bdf.bus], in i10nm_get_ddr_munits()
705 res_cfg->util_all_bdf.dev, in i10nm_get_ddr_munits()
706 res_cfg->util_all_bdf.fun); in i10nm_get_ddr_munits()
710 d->uracu = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->uracu_bdf.bus], in i10nm_get_ddr_munits()
711 res_cfg->uracu_bdf.dev, in i10nm_get_ddr_munits()
712 res_cfg->uracu_bdf.fun); in i10nm_get_ddr_munits()
725 for (lmc = 0, i = 0; i < res_cfg->ddr_imc_num; i++) { in i10nm_get_ddr_munits()
804 lmc = res_cfg->ddr_imc_num; in i10nm_get_hbm_munits()
806 for (i = 0; i < res_cfg->hbm_imc_num; i++) { in i10nm_get_hbm_munits()
807 mdev = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->hbm_mdev_bdf.bus], in i10nm_get_hbm_munits()
808 res_cfg->hbm_mdev_bdf.dev + i / 4, in i10nm_get_hbm_munits()
809 res_cfg->hbm_mdev_bdf.fun + i % 4); in i10nm_get_hbm_munits()
980 if (res_cfg->type != GNR) in i10nm_get_dimm_config()
1039 res_cfg = cfg; in i10nm_init()
1065 imc_num = res_cfg->ddr_imc_num + res_cfg->hbm_imc_num; in i10nm_init()
1111 if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) { in i10nm_init()
1131 if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) { in i10nm_exit()