Lines Matching +full:mic +full:- +full:offset
2 * Cell MIC driver for ECC counting
20 #include <asm/cell-regs.h>
36 struct cell_edac_priv *priv = mci->pvt_info; in cell_edac_count_ce()
37 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ce()
38 unsigned long address, pfn, offset, syndrome; in cell_edac_count_ce() local
40 dev_dbg(mci->pdev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n", in cell_edac_count_ce()
41 priv->node, chan, ar); in cell_edac_count_ce()
45 if (priv->chanmask == 0x3) in cell_edac_count_ce()
48 offset = address & ~PAGE_MASK; in cell_edac_count_ce()
53 csrow->first_page + pfn, offset, syndrome, in cell_edac_count_ce()
54 0, chan, -1, "", ""); in cell_edac_count_ce()
59 struct cell_edac_priv *priv = mci->pvt_info; in cell_edac_count_ue()
60 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ue()
61 unsigned long address, pfn, offset; in cell_edac_count_ue() local
63 dev_dbg(mci->pdev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n", in cell_edac_count_ue()
64 priv->node, chan, ar); in cell_edac_count_ue()
68 if (priv->chanmask == 0x3) in cell_edac_count_ue()
71 offset = address & ~PAGE_MASK; in cell_edac_count_ue()
75 csrow->first_page + pfn, offset, 0, in cell_edac_count_ue()
76 0, chan, -1, "", ""); in cell_edac_count_ue()
81 struct cell_edac_priv *priv = mci->pvt_info; in cell_edac_check()
84 fir = in_be64(&priv->regs->mic_fir); in cell_edac_check()
86 if (fir != priv->prev_fir) { in cell_edac_check()
87 dev_dbg(mci->pdev, "fir change : 0x%016lx\n", fir); in cell_edac_check()
88 priv->prev_fir = fir; in cell_edac_check()
91 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) { in cell_edac_check()
92 addreg = in_be64(&priv->regs->mic_df_ecc_address_0); in cell_edac_check()
96 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) { in cell_edac_check()
97 addreg = in_be64(&priv->regs->mic_df_ecc_address_1); in cell_edac_check()
101 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) { in cell_edac_check()
102 addreg = in_be64(&priv->regs->mic_df_ecc_address_0); in cell_edac_check()
106 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) { in cell_edac_check()
107 addreg = in_be64(&priv->regs->mic_df_ecc_address_1); in cell_edac_check()
117 out_be64(&priv->regs->mic_fir, fir); in cell_edac_check()
118 (void)in_be64(&priv->regs->mic_fir); in cell_edac_check()
122 fir = in_be64(&priv->regs->mic_fir); in cell_edac_check()
123 dev_dbg(mci->pdev, "fir clear : 0x%016lx\n", fir); in cell_edac_check()
130 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_init_csrows()
132 struct cell_edac_priv *priv = mci->pvt_info; in cell_edac_init_csrows()
146 if (of_node_to_nid(np) != priv->node) in cell_edac_init_csrows()
148 csrow->first_page = r.start >> PAGE_SHIFT; in cell_edac_init_csrows()
150 csrow->last_page = csrow->first_page + nr_pages - 1; in cell_edac_init_csrows()
152 for (j = 0; j < csrow->nr_channels; j++) { in cell_edac_init_csrows()
153 dimm = csrow->channels[j]->dimm; in cell_edac_init_csrows()
154 dimm->mtype = MEM_XDR; in cell_edac_init_csrows()
155 dimm->edac_mode = EDAC_SECDED; in cell_edac_init_csrows()
156 dimm->nr_pages = nr_pages / csrow->nr_channels; in cell_edac_init_csrows()
158 dev_dbg(mci->pdev, in cell_edac_init_csrows()
161 priv->node, priv->chanmask, in cell_edac_init_csrows()
162 csrow->first_page, nr_pages); in cell_edac_init_csrows()
177 regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id)); in cell_edac_probe()
179 return -ENODEV; in cell_edac_probe()
184 reg = in_be64(®s->mic_mnt_cfg); in cell_edac_probe()
185 dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg); in cell_edac_probe()
192 dev_warn(&pdev->dev, in cell_edac_probe()
194 return -ENODEV; in cell_edac_probe()
196 dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n", in cell_edac_probe()
197 in_be64(®s->mic_fir)); in cell_edac_probe()
208 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, in cell_edac_probe()
211 return -ENOMEM; in cell_edac_probe()
212 priv = mci->pvt_info; in cell_edac_probe()
213 priv->regs = regs; in cell_edac_probe()
214 priv->node = pdev->id; in cell_edac_probe()
215 priv->chanmask = chanmask; in cell_edac_probe()
216 mci->pdev = &pdev->dev; in cell_edac_probe()
217 mci->mtype_cap = MEM_FLAG_XDR; in cell_edac_probe()
218 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; in cell_edac_probe()
219 mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED; in cell_edac_probe()
220 mci->mod_name = "cell_edac"; in cell_edac_probe()
221 mci->ctl_name = "MIC"; in cell_edac_probe()
222 mci->dev_name = dev_name(&pdev->dev); in cell_edac_probe()
223 mci->edac_check = cell_edac_check; in cell_edac_probe()
229 dev_err(&pdev->dev, "failed to register with EDAC core\n"); in cell_edac_probe()
239 struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev); in cell_edac_remove()
246 .name = "cbe-mic",
281 MODULE_DESCRIPTION("ECC counting for Cell MIC");