379 		csbase		= pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
380 		csmask		= pvt->csels[dct].csmasks[csrow];  in get_cs_base_and_mask()
391 		csbase          = pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
392 		csmask          = pvt->csels[dct].csmasks[csrow >> 1];  in get_cs_base_and_mask()
407 		csbase		= pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
408 		csmask		= pvt->csels[dct].csmasks[csrow >> 1];  in get_cs_base_and_mask()
429 	for (i = 0; i < pvt->csels[dct].b_cnt; i++)
432 	pvt->csels[dct].csbases[i]
435 	for (i = 0; i < pvt->csels[dct].m_cnt; i++)
1105 	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;  in dct_debug_display_dimm_sizes()
1121 				 pvt->csels[1].csbases :  in dct_debug_display_dimm_sizes()
1122 				 pvt->csels[0].csbases;  in dct_debug_display_dimm_sizes()
1125 		dcsb = pvt->csels[1].csbases;  in dct_debug_display_dimm_sizes()
1164 		u32 dcsm = pvt->csels[chan].csmasks[0];  in debug_dump_dramcfg_low()
1224 	    pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) {  in umc_get_cs_mode()
1312 		addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];  in umc_addr_mask_to_cs_size()
1314 		addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];  in umc_addr_mask_to_cs_size()
1411 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;  in dct_prep_chip_selects()
1412 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;  in dct_prep_chip_selects()
1414 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;  in dct_prep_chip_selects()
1415 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;  in dct_prep_chip_selects()
1417 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;  in dct_prep_chip_selects()
1418 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;  in dct_prep_chip_selects()
1427 		pvt->csels[umc].b_cnt = 4;  in umc_prep_chip_selects()
1428 		pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2;  in umc_prep_chip_selects()
1448 			base = &pvt->csels[umc].csbases[cs];  in umc_read_base_mask()
1449 			base_sec = &pvt->csels[umc].csbases_sec[cs];  in umc_read_base_mask()
1471 			mask = &pvt->csels[umc].csmasks[cs];  in umc_read_base_mask()
1472 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];  in umc_read_base_mask()
1502 		u32 *base0 = &pvt->csels[0].csbases[cs];  in dct_read_base_mask()
1503 		u32 *base1 = &pvt->csels[1].csbases[cs];  in dct_read_base_mask()
1521 		u32 *mask0 = &pvt->csels[0].csmasks[cs];  in dct_read_base_mask()
1522 		u32 *mask1 = &pvt->csels[1].csmasks[cs];  in dct_read_base_mask()
1608 		dcsm = pvt->csels[0].csmasks[0];  in dct_determine_memory_type()
1973 	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];  in f15_m60h_dbam_to_chip_select()
3530 	u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr];  in gpu_addr_mask_to_cs_size()
3683 			base = &pvt->csels[umc].csbases[cs];  in gpu_read_base_mask()
3691 			mask = &pvt->csels[umc].csmasks[cs];  in gpu_read_base_mask()
3706 		pvt->csels[umc].b_cnt = 8;  in gpu_prep_chip_selects()
3707 		pvt->csels[umc].m_cnt = 8;  in gpu_prep_chip_selects()
3954 			      : pvt->csels[0].b_cnt;  in get_layer_size()
3956 		return is_gpu ? pvt->csels[0].b_cnt  in get_layer_size()