Lines Matching full:pvt
17 static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg) in get_umc_reg() argument
19 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
102 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
106 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
107 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
109 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
126 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
129 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
142 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
154 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
155 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
166 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
187 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) in __set_scrub_rate() argument
215 if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
216 f15h_select_dct(pvt, 0); in __set_scrub_rate()
217 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
218 f15h_select_dct(pvt, 1); in __set_scrub_rate()
219 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
221 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
232 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate() local
235 if (pvt->fam == 0xf) in set_scrub_rate()
238 if (pvt->fam == 0x15) { in set_scrub_rate()
240 if (pvt->model < 0x10) in set_scrub_rate()
241 f15h_select_dct(pvt, 0); in set_scrub_rate()
243 if (pvt->model == 0x60) in set_scrub_rate()
246 return __set_scrub_rate(pvt, bw, min_scrubrate); in set_scrub_rate()
251 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate() local
255 if (pvt->fam == 0x15) { in get_scrub_rate()
257 if (pvt->model < 0x10) in get_scrub_rate()
258 f15h_select_dct(pvt, 0); in get_scrub_rate()
260 if (pvt->model == 0x60) in get_scrub_rate()
261 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
263 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
265 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
283 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) in base_limit_match() argument
295 return ((addr >= get_dram_base(pvt, nid)) && in base_limit_match()
296 (addr <= get_dram_limit(pvt, nid))); in base_limit_match()
308 struct amd64_pvt *pvt; in find_mc_by_sys_addr() local
316 pvt = mci->pvt_info; in find_mc_by_sys_addr()
323 intlv_en = dram_intlv_en(pvt, 0); in find_mc_by_sys_addr()
327 if (base_limit_match(pvt, sys_addr, node_id)) in find_mc_by_sys_addr()
343 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) in find_mc_by_sys_addr()
351 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { in find_mc_by_sys_addr()
372 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
378 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
379 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
380 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
389 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
390 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
391 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
392 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
407 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
408 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
411 if (pvt->fam == 0x15) in get_cs_base_and_mask()
428 #define for_each_chip_select(i, dct, pvt) \ argument
429 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
431 #define chip_select_base(i, dct, pvt) \ argument
432 pvt->csels[dct].csbases[i]
434 #define for_each_chip_select_mask(i, dct, pvt) \ argument
435 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
438 for (i = 0; i < pvt->max_mcs; i++)
446 struct amd64_pvt *pvt; in input_addr_to_csrow() local
450 pvt = mci->pvt_info; in input_addr_to_csrow()
452 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
453 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
456 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
463 pvt->mc_node_id); in input_addr_to_csrow()
469 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
493 struct amd64_pvt *pvt = mci->pvt_info; in get_dram_hole_info() local
496 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in get_dram_hole_info()
498 pvt->ext_model, pvt->mc_node_id); in get_dram_hole_info()
503 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in get_dram_hole_info()
508 if (!dhar_valid(pvt)) { in get_dram_hole_info()
510 pvt->mc_node_id); in get_dram_hole_info()
532 *hole_base = dhar_base(pvt); in get_dram_hole_info()
535 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in get_dram_hole_info()
536 : k8_dhar_offset(pvt); in get_dram_hole_info()
539 pvt->mc_node_id, (unsigned long)*hole_base, in get_dram_hole_info()
551 struct amd64_pvt *pvt = mci->pvt_info; \
553 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
602 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_show() local
603 return sprintf(buf, "0x%x\n", pvt->injection.section); in inject_section_show()
617 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_store() local
630 pvt->injection.section = (u32) value; in inject_section_store()
638 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_show() local
639 return sprintf(buf, "0x%x\n", pvt->injection.word); in inject_word_show()
653 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_store() local
666 pvt->injection.word = (u32) value; in inject_word_store()
675 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_show() local
676 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in inject_ecc_vector_show()
689 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_store() local
702 pvt->injection.bit_map = (u32) value; in inject_ecc_vector_store()
707 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
715 struct amd64_pvt *pvt = mci->pvt_info; in inject_read_store() local
725 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_read_store()
727 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_read_store()
729 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); in inject_read_store()
732 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_read_store()
740 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
748 struct amd64_pvt *pvt = mci->pvt_info; in inject_write_store() local
758 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_write_store()
760 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_write_store()
762 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); in inject_write_store()
771 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_write_store()
775 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); in inject_write_store()
811 struct amd64_pvt *pvt = mci->pvt_info; in inj_is_visible() local
814 if (pvt->fam >= 0x10 && pvt->fam <= 0x16) in inj_is_visible()
857 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr() local
861 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
912 struct amd64_pvt *pvt; in dram_addr_to_input_addr() local
916 pvt = mci->pvt_info; in dram_addr_to_input_addr()
922 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); in dram_addr_to_input_addr()
999 static int gpu_get_node_map(struct amd64_pvt *pvt) in gpu_get_node_map() argument
1010 if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3) in gpu_get_node_map()
1062 static unsigned long dct_determine_edac_cap(struct amd64_pvt *pvt) in dct_determine_edac_cap() argument
1067 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in dct_determine_edac_cap()
1071 if (pvt->dclr0 & BIT(bit)) in dct_determine_edac_cap()
1077 static unsigned long umc_determine_edac_cap(struct amd64_pvt *pvt) in umc_determine_edac_cap() argument
1083 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1089 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1103 static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in dct_debug_display_dimm_sizes() argument
1105 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1106 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1109 if (pvt->fam == 0xf) { in dct_debug_display_dimm_sizes()
1111 if (pvt->ext_model < K8_REV_F) in dct_debug_display_dimm_sizes()
1117 if (pvt->fam == 0x10) { in dct_debug_display_dimm_sizes()
1118 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in dct_debug_display_dimm_sizes()
1119 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1120 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? in dct_debug_display_dimm_sizes()
1121 pvt->csels[1].csbases : in dct_debug_display_dimm_sizes()
1122 pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1124 dbam = pvt->dbam0; in dct_debug_display_dimm_sizes()
1125 dcsb = pvt->csels[1].csbases; in dct_debug_display_dimm_sizes()
1142 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1148 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1159 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
1163 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1164 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
1180 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
1200 static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) in umc_get_cs_mode() argument
1205 if (csrow_enabled(2 * dimm, ctrl, pvt)) in umc_get_cs_mode()
1208 if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) in umc_get_cs_mode()
1212 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) in umc_get_cs_mode()
1220 for_each_chip_select(base, ctrl, pvt) in umc_get_cs_mode()
1221 count += csrow_enabled(base, ctrl, pvt); in umc_get_cs_mode()
1224 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { in umc_get_cs_mode()
1268 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in umc_addr_mask_to_cs_size() argument
1307 if (!pvt->flags.zn_regs_v2) in umc_addr_mask_to_cs_size()
1312 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1314 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1319 static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in umc_debug_display_dimm_sizes() argument
1329 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt); in umc_debug_display_dimm_sizes()
1331 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0); in umc_debug_display_dimm_sizes()
1332 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1); in umc_debug_display_dimm_sizes()
1340 static void umc_dump_misc_regs(struct amd64_pvt *pvt) in umc_dump_misc_regs() argument
1346 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1364 umc_debug_display_dimm_sizes(pvt, i); in umc_dump_misc_regs()
1368 static void dct_dump_misc_regs(struct amd64_pvt *pvt) in dct_dump_misc_regs() argument
1370 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in dct_dump_misc_regs()
1373 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in dct_dump_misc_regs()
1376 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in dct_dump_misc_regs()
1377 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in dct_dump_misc_regs()
1379 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in dct_dump_misc_regs()
1381 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in dct_dump_misc_regs()
1384 pvt->dhar, dhar_base(pvt), in dct_dump_misc_regs()
1385 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in dct_dump_misc_regs()
1386 : f10_dhar_offset(pvt)); in dct_dump_misc_regs()
1388 dct_debug_display_dimm_sizes(pvt, 0); in dct_dump_misc_regs()
1391 if (pvt->fam == 0xf) in dct_dump_misc_regs()
1394 dct_debug_display_dimm_sizes(pvt, 1); in dct_dump_misc_regs()
1397 if (!dct_ganging_enabled(pvt)) in dct_dump_misc_regs()
1398 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in dct_dump_misc_regs()
1400 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); in dct_dump_misc_regs()
1402 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dct_dump_misc_regs()
1408 static void dct_prep_chip_selects(struct amd64_pvt *pvt) in dct_prep_chip_selects() argument
1410 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in dct_prep_chip_selects()
1411 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1412 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in dct_prep_chip_selects()
1413 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in dct_prep_chip_selects()
1414 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in dct_prep_chip_selects()
1415 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in dct_prep_chip_selects()
1417 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1418 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in dct_prep_chip_selects()
1422 static void umc_prep_chip_selects(struct amd64_pvt *pvt) in umc_prep_chip_selects() argument
1427 pvt->csels[umc].b_cnt = 4; in umc_prep_chip_selects()
1428 pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2; in umc_prep_chip_selects()
1432 static void umc_read_base_mask(struct amd64_pvt *pvt) in umc_read_base_mask() argument
1447 for_each_chip_select(cs, umc, pvt) { in umc_read_base_mask()
1448 base = &pvt->csels[umc].csbases[cs]; in umc_read_base_mask()
1449 base_sec = &pvt->csels[umc].csbases_sec[cs]; in umc_read_base_mask()
1454 if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) { in umc_read_base_mask()
1460 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) { in umc_read_base_mask()
1468 umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(pvt, UMCCH_ADDR_MASK_SEC); in umc_read_base_mask()
1470 for_each_chip_select_mask(cs, umc, pvt) { in umc_read_base_mask()
1471 mask = &pvt->csels[umc].csmasks[cs]; in umc_read_base_mask()
1472 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in umc_read_base_mask()
1477 if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) { in umc_read_base_mask()
1483 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) { in umc_read_base_mask()
1495 static void dct_read_base_mask(struct amd64_pvt *pvt) in dct_read_base_mask() argument
1499 for_each_chip_select(cs, 0, pvt) { in dct_read_base_mask()
1502 u32 *base0 = &pvt->csels[0].csbases[cs]; in dct_read_base_mask()
1503 u32 *base1 = &pvt->csels[1].csbases[cs]; in dct_read_base_mask()
1505 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) in dct_read_base_mask()
1509 if (pvt->fam == 0xf) in dct_read_base_mask()
1512 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) in dct_read_base_mask()
1514 cs, *base1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1518 for_each_chip_select_mask(cs, 0, pvt) { in dct_read_base_mask()
1521 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in dct_read_base_mask()
1522 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in dct_read_base_mask()
1524 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) in dct_read_base_mask()
1528 if (pvt->fam == 0xf) in dct_read_base_mask()
1531 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in dct_read_base_mask()
1533 cs, *mask1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1538 static void umc_determine_memory_type(struct amd64_pvt *pvt) in umc_determine_memory_type() argument
1544 umc = &pvt->umc[i]; in umc_determine_memory_type()
1555 if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { in umc_determine_memory_type()
1575 static void dct_determine_memory_type(struct amd64_pvt *pvt) in dct_determine_memory_type() argument
1579 switch (pvt->fam) { in dct_determine_memory_type()
1581 if (pvt->ext_model >= K8_REV_F) in dct_determine_memory_type()
1584 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in dct_determine_memory_type()
1588 if (pvt->dchr0 & DDR3_MODE) in dct_determine_memory_type()
1591 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in dct_determine_memory_type()
1595 if (pvt->model < 0x60) in dct_determine_memory_type()
1607 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); in dct_determine_memory_type()
1608 dcsm = pvt->csels[0].csmasks[0]; in dct_determine_memory_type()
1611 pvt->dram_type = MEM_DDR4; in dct_determine_memory_type()
1612 else if (pvt->dclr0 & BIT(16)) in dct_determine_memory_type()
1613 pvt->dram_type = MEM_DDR3; in dct_determine_memory_type()
1615 pvt->dram_type = MEM_LRDDR3; in dct_determine_memory_type()
1617 pvt->dram_type = MEM_RDDR3; in dct_determine_memory_type()
1625 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in dct_determine_memory_type()
1626 pvt->dram_type = MEM_EMPTY; in dct_determine_memory_type()
1629 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in dct_determine_memory_type()
1633 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in dct_determine_memory_type()
1637 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) in get_error_address() argument
1649 pvt = mci->pvt_info; in get_error_address()
1651 if (pvt->fam == 0xf) { in get_error_address()
1661 if (pvt->fam == 0x15) { in get_error_address()
1670 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1685 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1718 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) in read_dram_base_limit_regs() argument
1726 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1727 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1729 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1732 if (!dram_rw(pvt, range)) in read_dram_base_limit_regs()
1735 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1736 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1739 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1742 nb = node_to_amd_nb(dram_dst_node(pvt, range)); in read_dram_base_limit_regs()
1746 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1748 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1759 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1762 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1764 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1767 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1775 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow() local
1799 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1840 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1843 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1845 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1849 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1944 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1947 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1951 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1960 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1969 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1973 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1977 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1982 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
2002 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
2014 static void read_dram_ctl_register(struct amd64_pvt *pvt) in read_dram_ctl_register() argument
2017 if (pvt->fam == 0xf) in read_dram_ctl_register()
2020 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
2022 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
2025 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
2027 if (!dct_ganging_enabled(pvt)) in read_dram_ctl_register()
2029 (dct_high_range_enabled(pvt) ? "yes" : "no")); in read_dram_ctl_register()
2032 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
2033 (dct_memory_cleared(pvt) ? "yes" : "no")); in read_dram_ctl_register()
2037 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
2038 dct_sel_interleave_addr(pvt)); in read_dram_ctl_register()
2041 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
2048 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f15_m30h_determine_channel() argument
2062 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_determine_channel()
2079 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f1x_determine_channel() argument
2082 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
2084 if (dct_ganging_enabled(pvt)) in f1x_determine_channel()
2093 if (dct_interleave_enabled(pvt)) { in f1x_determine_channel()
2094 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f1x_determine_channel()
2116 if (dct_high_range_enabled(pvt)) in f1x_determine_channel()
2123 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, in f1x_get_norm_dct_addr() argument
2128 u64 dram_base = get_dram_base(pvt, range); in f1x_get_norm_dct_addr()
2129 u64 hole_off = f10_dhar_offset(pvt); in f1x_get_norm_dct_addr()
2130 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
2145 dct_sel_base_addr < dhar_base(pvt)) && in f1x_get_norm_dct_addr()
2146 dhar_valid(pvt) && in f1x_get_norm_dct_addr()
2161 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) in f1x_get_norm_dct_addr()
2174 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
2178 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
2179 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
2181 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
2182 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
2202 struct amd64_pvt *pvt; in f1x_lookup_addr_in_dct() local
2211 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
2215 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
2216 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
2219 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2230 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
2234 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
2248 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) in f1x_swap_interleaved_region() argument
2252 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
2254 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
2258 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
2278 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f1x_match_to_this_node() argument
2287 u8 node_id = dram_dst_node(pvt, range); in f1x_match_to_this_node()
2288 u8 intlv_en = dram_intlv_en(pvt, range); in f1x_match_to_this_node()
2289 u32 intlv_sel = dram_intlv_sel(pvt, range); in f1x_match_to_this_node()
2292 range, sys_addr, get_dram_limit(pvt, range)); in f1x_match_to_this_node()
2294 if (dhar_valid(pvt) && in f1x_match_to_this_node()
2295 dhar_base(pvt) <= sys_addr && in f1x_match_to_this_node()
2305 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); in f1x_match_to_this_node()
2307 dct_sel_base = dct_sel_baseaddr(pvt); in f1x_match_to_this_node()
2313 if (dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
2314 !dct_ganging_enabled(pvt) && in f1x_match_to_this_node()
2318 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); in f1x_match_to_this_node()
2320 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, in f1x_match_to_this_node()
2329 if (dct_interleave_enabled(pvt) && in f1x_match_to_this_node()
2330 !dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
2331 !dct_ganging_enabled(pvt)) { in f1x_match_to_this_node()
2333 if (dct_sel_interleave_addr(pvt) != 1) { in f1x_match_to_this_node()
2334 if (dct_sel_interleave_addr(pvt) == 0x3) in f1x_match_to_this_node()
2358 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f15_m30h_match_to_this_node() argument
2368 u64 dhar_offset = f10_dhar_offset(pvt); in f15_m30h_match_to_this_node()
2369 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_match_to_this_node()
2370 u8 node_id = dram_dst_node(pvt, range); in f15_m30h_match_to_this_node()
2371 u8 intlv_en = dram_intlv_en(pvt, range); in f15_m30h_match_to_this_node()
2373 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2374 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2380 range, sys_addr, get_dram_limit(pvt, range)); in f15_m30h_match_to_this_node()
2382 if (!(get_dram_base(pvt, range) <= sys_addr) && in f15_m30h_match_to_this_node()
2383 !(get_dram_limit(pvt, range) >= sys_addr)) in f15_m30h_match_to_this_node()
2386 if (dhar_valid(pvt) && in f15_m30h_match_to_this_node()
2387 dhar_base(pvt) <= sys_addr && in f15_m30h_match_to_this_node()
2395 dct_base = (u64) dct_sel_baseaddr(pvt); in f15_m30h_match_to_this_node()
2409 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2410 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en); in f15_m30h_match_to_this_node()
2412 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, in f15_m30h_match_to_this_node()
2452 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2458 f15h_select_dct(pvt, channel); in f15_m30h_match_to_this_node()
2467 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2480 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, in f1x_translate_sysaddr_to_cs() argument
2488 if (!dram_rw(pvt, range)) in f1x_translate_sysaddr_to_cs()
2491 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2492 cs_found = f15_m30h_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2496 else if ((get_dram_base(pvt, range) <= sys_addr) && in f1x_translate_sysaddr_to_cs()
2497 (get_dram_limit(pvt, range) >= sys_addr)) { in f1x_translate_sysaddr_to_cs()
2498 cs_found = f1x_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2517 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow() local
2521 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2532 if (dct_ganging_enabled(pvt)) in f1x_map_sysaddr_to_csrow()
2673 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome() local
2676 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2679 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2680 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2683 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2685 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2689 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2742 struct amd64_pvt *pvt; in decode_bus_error() local
2753 pvt = mci->pvt_info; in decode_bus_error()
2765 sys_addr = get_error_address(pvt, m); in decode_bus_error()
2770 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2798 struct amd64_pvt *pvt; in decode_umc_error() local
2808 pvt = mci->pvt_info; in decode_umc_error()
2829 pvt->ops->get_err_info(m, &err); in decode_umc_error()
2848 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2852 reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) in reserve_mc_sibling_devs() argument
2855 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2856 if (!pvt->F1) { in reserve_mc_sibling_devs()
2862 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2863 if (!pvt->F2) { in reserve_mc_sibling_devs()
2864 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2865 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2872 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2874 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2875 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2876 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2881 static void determine_ecc_sym_sz(struct amd64_pvt *pvt) in determine_ecc_sym_sz() argument
2883 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2885 if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2888 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2890 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2891 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2894 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2895 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2902 static void umc_read_mc_regs(struct amd64_pvt *pvt) in umc_read_mc_regs() argument
2904 u8 nid = pvt->mc_node_id; in umc_read_mc_regs()
2912 umc = &pvt->umc[i]; in umc_read_mc_regs()
2914 if (!amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &tmp)) in umc_read_mc_regs()
2935 static void dct_read_mc_regs(struct amd64_pvt *pvt) in dct_read_mc_regs() argument
2944 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in dct_read_mc_regs()
2945 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in dct_read_mc_regs()
2950 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in dct_read_mc_regs()
2951 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in dct_read_mc_regs()
2956 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in dct_read_mc_regs()
2958 read_dram_ctl_register(pvt); in dct_read_mc_regs()
2964 read_dram_base_limit_regs(pvt, range); in dct_read_mc_regs()
2966 rw = dram_rw(pvt, range); in dct_read_mc_regs()
2972 get_dram_base(pvt, range), in dct_read_mc_regs()
2973 get_dram_limit(pvt, range)); in dct_read_mc_regs()
2976 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", in dct_read_mc_regs()
2979 dram_intlv_sel(pvt, range), in dct_read_mc_regs()
2980 dram_dst_node(pvt, range)); in dct_read_mc_regs()
2983 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in dct_read_mc_regs()
2984 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in dct_read_mc_regs()
2986 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in dct_read_mc_regs()
2988 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in dct_read_mc_regs()
2989 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in dct_read_mc_regs()
2991 if (!dct_ganging_enabled(pvt)) { in dct_read_mc_regs()
2992 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in dct_read_mc_regs()
2993 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in dct_read_mc_regs()
2996 determine_ecc_sym_sz(pvt); in dct_read_mc_regs()
3033 static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in dct_get_csrow_nr_pages() argument
3035 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in dct_get_csrow_nr_pages()
3041 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3051 static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in umc_get_csrow_nr_pages() argument
3056 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt); in umc_get_csrow_nr_pages()
3058 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in umc_get_csrow_nr_pages()
3070 struct amd64_pvt *pvt = mci->pvt_info; in umc_init_csrows() local
3090 for_each_chip_select(cs, umc, pvt) { in umc_init_csrows()
3091 if (!csrow_enabled(cs, umc, pvt)) in umc_init_csrows()
3097 pvt->mc_node_id, cs); in umc_init_csrows()
3099 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs); in umc_init_csrows()
3100 dimm->mtype = pvt->umc[umc].dram_type; in umc_init_csrows()
3114 struct amd64_pvt *pvt = mci->pvt_info; in dct_init_csrows() local
3122 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in dct_init_csrows()
3124 pvt->nbcfg = val; in dct_init_csrows()
3127 pvt->mc_node_id, val, in dct_init_csrows()
3133 for_each_chip_select(i, 0, pvt) { in dct_init_csrows()
3134 bool row_dct0 = !!csrow_enabled(i, 0, pvt); in dct_init_csrows()
3137 if (pvt->fam != 0xf) in dct_init_csrows()
3138 row_dct1 = !!csrow_enabled(i, 1, pvt); in dct_init_csrows()
3146 pvt->mc_node_id, i); in dct_init_csrows()
3149 nr_pages = dct_get_csrow_nr_pages(pvt, 0, i); in dct_init_csrows()
3154 if (pvt->fam != 0xf && row_dct1) { in dct_init_csrows()
3155 int row_dct1_pages = dct_get_csrow_nr_pages(pvt, 1, i); in dct_init_csrows()
3164 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in dct_init_csrows()
3165 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in dct_init_csrows()
3170 for (j = 0; j < pvt->max_mcs; j++) { in dct_init_csrows()
3172 dimm->mtype = pvt->dram_type; in dct_init_csrows()
3339 static bool dct_ecc_enabled(struct amd64_pvt *pvt) in dct_ecc_enabled() argument
3341 u16 nid = pvt->mc_node_id; in dct_ecc_enabled()
3346 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in dct_ecc_enabled()
3363 static bool umc_ecc_enabled(struct amd64_pvt *pvt) in umc_ecc_enabled() argument
3366 u16 nid = pvt->mc_node_id; in umc_ecc_enabled()
3371 umc = &pvt->umc[i]; in umc_ecc_enabled()
3398 umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) in umc_determine_edac_ctl_cap() argument
3403 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in umc_determine_edac_ctl_cap()
3404 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in umc_determine_edac_ctl_cap()
3405 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in umc_determine_edac_ctl_cap()
3407 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in umc_determine_edac_ctl_cap()
3408 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in umc_determine_edac_ctl_cap()
3430 struct amd64_pvt *pvt = mci->pvt_info; in dct_setup_mci_misc_attrs() local
3435 if (pvt->nbcap & NBCAP_SECDED) in dct_setup_mci_misc_attrs()
3438 if (pvt->nbcap & NBCAP_CHIPKILL) in dct_setup_mci_misc_attrs()
3441 mci->edac_cap = dct_determine_edac_cap(pvt); in dct_setup_mci_misc_attrs()
3443 mci->ctl_name = pvt->ctl_name; in dct_setup_mci_misc_attrs()
3444 mci->dev_name = pci_name(pvt->F3); in dct_setup_mci_misc_attrs()
3456 struct amd64_pvt *pvt = mci->pvt_info; in umc_setup_mci_misc_attrs() local
3461 umc_determine_edac_ctl_cap(mci, pvt); in umc_setup_mci_misc_attrs()
3463 mci->edac_cap = umc_determine_edac_cap(pvt); in umc_setup_mci_misc_attrs()
3465 mci->ctl_name = pvt->ctl_name; in umc_setup_mci_misc_attrs()
3466 mci->dev_name = pci_name(pvt->F3); in umc_setup_mci_misc_attrs()
3472 static int dct_hw_info_get(struct amd64_pvt *pvt) in dct_hw_info_get() argument
3474 int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id); in dct_hw_info_get()
3479 dct_prep_chip_selects(pvt); in dct_hw_info_get()
3480 dct_read_base_mask(pvt); in dct_hw_info_get()
3481 dct_read_mc_regs(pvt); in dct_hw_info_get()
3482 dct_determine_memory_type(pvt); in dct_hw_info_get()
3487 static int umc_hw_info_get(struct amd64_pvt *pvt) in umc_hw_info_get() argument
3489 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in umc_hw_info_get()
3490 if (!pvt->umc) in umc_hw_info_get()
3493 umc_prep_chip_selects(pvt); in umc_hw_info_get()
3494 umc_read_base_mask(pvt); in umc_hw_info_get()
3495 umc_read_mc_regs(pvt); in umc_hw_info_get()
3496 umc_determine_memory_type(pvt); in umc_hw_info_get()
3527 static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in gpu_addr_mask_to_cs_size() argument
3530 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; in gpu_addr_mask_to_cs_size()
3535 static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in gpu_debug_display_dimm_sizes() argument
3543 for_each_chip_select(cs, ctrl, pvt) { in gpu_debug_display_dimm_sizes()
3544 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs); in gpu_debug_display_dimm_sizes()
3549 static void gpu_dump_misc_regs(struct amd64_pvt *pvt) in gpu_dump_misc_regs() argument
3555 umc = &pvt->umc[i]; in gpu_dump_misc_regs()
3562 gpu_debug_display_dimm_sizes(pvt, i); in gpu_dump_misc_regs()
3566 static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in gpu_get_csrow_nr_pages() argument
3571 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in gpu_get_csrow_nr_pages()
3582 struct amd64_pvt *pvt = mci->pvt_info; in gpu_init_csrows() local
3587 for_each_chip_select(cs, umc, pvt) { in gpu_init_csrows()
3588 if (!csrow_enabled(cs, umc, pvt)) in gpu_init_csrows()
3594 pvt->mc_node_id, cs); in gpu_init_csrows()
3596 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs); in gpu_init_csrows()
3598 dimm->mtype = pvt->dram_type; in gpu_init_csrows()
3607 struct amd64_pvt *pvt = mci->pvt_info; in gpu_setup_mci_misc_attrs() local
3614 mci->ctl_name = pvt->ctl_name; in gpu_setup_mci_misc_attrs()
3615 mci->dev_name = pci_name(pvt->F3); in gpu_setup_mci_misc_attrs()
3622 static bool gpu_ecc_enabled(struct amd64_pvt *pvt) in gpu_ecc_enabled() argument
3627 static inline u32 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel) in gpu_get_umc_base() argument
3649 return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12); in gpu_get_umc_base()
3652 static void gpu_read_mc_regs(struct amd64_pvt *pvt) in gpu_read_mc_regs() argument
3654 u8 nid = pvt->mc_node_id; in gpu_read_mc_regs()
3660 umc_base = gpu_get_umc_base(pvt, i, 0); in gpu_read_mc_regs()
3661 umc = &pvt->umc[i]; in gpu_read_mc_regs()
3674 static void gpu_read_base_mask(struct amd64_pvt *pvt) in gpu_read_base_mask() argument
3681 for_each_chip_select(cs, umc, pvt) { in gpu_read_base_mask()
3682 base_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_BASE_ADDR; in gpu_read_base_mask()
3683 base = &pvt->csels[umc].csbases[cs]; in gpu_read_base_mask()
3685 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) { in gpu_read_base_mask()
3690 mask_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_ADDR_MASK; in gpu_read_base_mask()
3691 mask = &pvt->csels[umc].csmasks[cs]; in gpu_read_base_mask()
3693 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) { in gpu_read_base_mask()
3701 static void gpu_prep_chip_selects(struct amd64_pvt *pvt) in gpu_prep_chip_selects() argument
3706 pvt->csels[umc].b_cnt = 8; in gpu_prep_chip_selects()
3707 pvt->csels[umc].m_cnt = 8; in gpu_prep_chip_selects()
3711 static int gpu_hw_info_get(struct amd64_pvt *pvt) in gpu_hw_info_get() argument
3715 ret = gpu_get_node_map(pvt); in gpu_hw_info_get()
3719 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in gpu_hw_info_get()
3720 if (!pvt->umc) in gpu_hw_info_get()
3723 gpu_prep_chip_selects(pvt); in gpu_hw_info_get()
3724 gpu_read_base_mask(pvt); in gpu_hw_info_get()
3725 gpu_read_mc_regs(pvt); in gpu_hw_info_get()
3730 static void hw_info_put(struct amd64_pvt *pvt) in hw_info_put() argument
3732 pci_dev_put(pvt->F1); in hw_info_put()
3733 pci_dev_put(pvt->F2); in hw_info_put()
3734 kfree(pvt->umc); in hw_info_put()
3763 static int per_family_init(struct amd64_pvt *pvt) in per_family_init() argument
3765 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3766 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3767 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3768 pvt->fam = boot_cpu_data.x86; in per_family_init()
3769 pvt->max_mcs = 2; in per_family_init()
3775 if (pvt->fam >= 0x17) in per_family_init()
3776 pvt->ops = &umc_ops; in per_family_init()
3778 pvt->ops = &dct_ops; in per_family_init()
3780 switch (pvt->fam) { in per_family_init()
3782 pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ? in per_family_init()
3784 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; in per_family_init()
3785 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; in per_family_init()
3786 pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; in per_family_init()
3787 pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; in per_family_init()
3791 pvt->ctl_name = "F10h"; in per_family_init()
3792 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; in per_family_init()
3793 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; in per_family_init()
3794 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; in per_family_init()
3798 switch (pvt->model) { in per_family_init()
3800 pvt->ctl_name = "F15h_M30h"; in per_family_init()
3801 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; in per_family_init()
3802 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; in per_family_init()
3805 pvt->ctl_name = "F15h_M60h"; in per_family_init()
3806 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; in per_family_init()
3807 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; in per_family_init()
3808 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; in per_family_init()
3814 pvt->ctl_name = "F15h"; in per_family_init()
3815 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; in per_family_init()
3816 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; in per_family_init()
3817 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; in per_family_init()
3823 switch (pvt->model) { in per_family_init()
3825 pvt->ctl_name = "F16h_M30h"; in per_family_init()
3826 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; in per_family_init()
3827 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; in per_family_init()
3830 pvt->ctl_name = "F16h"; in per_family_init()
3831 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; in per_family_init()
3832 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; in per_family_init()
3838 switch (pvt->model) { in per_family_init()
3840 pvt->ctl_name = "F17h_M10h"; in per_family_init()
3843 pvt->ctl_name = "F17h_M30h"; in per_family_init()
3844 pvt->max_mcs = 8; in per_family_init()
3847 pvt->ctl_name = "F17h_M60h"; in per_family_init()
3850 pvt->ctl_name = "F17h_M70h"; in per_family_init()
3853 pvt->ctl_name = "F17h"; in per_family_init()
3859 pvt->ctl_name = "F18h"; in per_family_init()
3863 switch (pvt->model) { in per_family_init()
3865 pvt->ctl_name = "F19h"; in per_family_init()
3866 pvt->max_mcs = 8; in per_family_init()
3869 pvt->ctl_name = "F19h_M10h"; in per_family_init()
3870 pvt->max_mcs = 12; in per_family_init()
3871 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3874 pvt->ctl_name = "F19h_M20h"; in per_family_init()
3877 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) { in per_family_init()
3878 pvt->ctl_name = "MI200"; in per_family_init()
3879 pvt->max_mcs = 4; in per_family_init()
3880 pvt->dram_type = MEM_HBM2; in per_family_init()
3881 pvt->gpu_umc_base = 0x50000; in per_family_init()
3882 pvt->ops = &gpu_ops; in per_family_init()
3884 pvt->ctl_name = "F19h_M30h"; in per_family_init()
3885 pvt->max_mcs = 8; in per_family_init()
3889 pvt->ctl_name = "F19h_M50h"; in per_family_init()
3892 pvt->ctl_name = "F19h_M60h"; in per_family_init()
3893 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3896 pvt->ctl_name = "F19h_M70h"; in per_family_init()
3897 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3900 pvt->ctl_name = "F19h_M90h"; in per_family_init()
3901 pvt->max_mcs = 4; in per_family_init()
3902 pvt->dram_type = MEM_HBM3; in per_family_init()
3903 pvt->gpu_umc_base = 0x90000; in per_family_init()
3904 pvt->ops = &gpu_ops; in per_family_init()
3907 pvt->ctl_name = "F19h_MA0h"; in per_family_init()
3908 pvt->max_mcs = 12; in per_family_init()
3909 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3915 switch (pvt->model) { in per_family_init()
3917 pvt->ctl_name = "F1Ah"; in per_family_init()
3918 pvt->max_mcs = 12; in per_family_init()
3919 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3922 pvt->ctl_name = "F1Ah_M40h"; in per_family_init()
3923 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3948 static unsigned int get_layer_size(struct amd64_pvt *pvt, u8 layer) in get_layer_size() argument
3950 bool is_gpu = (pvt->ops == &gpu_ops); in get_layer_size()
3953 return is_gpu ? pvt->max_mcs in get_layer_size()
3954 : pvt->csels[0].b_cnt; in get_layer_size()
3956 return is_gpu ? pvt->csels[0].b_cnt in get_layer_size()
3957 : pvt->max_mcs; in get_layer_size()
3960 static int init_one_instance(struct amd64_pvt *pvt) in init_one_instance() argument
3967 layers[0].size = get_layer_size(pvt, 0); in init_one_instance()
3970 layers[1].size = get_layer_size(pvt, 1); in init_one_instance()
3973 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3977 mci->pvt_info = pvt; in init_one_instance()
3978 mci->pdev = &pvt->F3->dev; in init_one_instance()
3980 pvt->ops->setup_mci_misc_attrs(mci); in init_one_instance()
3992 static bool instance_has_memory(struct amd64_pvt *pvt) in instance_has_memory() argument
3997 for (dct = 0; dct < pvt->max_mcs; dct++) { in instance_has_memory()
3998 for_each_chip_select(cs, dct, pvt) in instance_has_memory()
3999 cs_enabled |= csrow_enabled(cs, dct, pvt); in instance_has_memory()
4008 struct amd64_pvt *pvt = NULL; in probe_one_instance() local
4019 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); in probe_one_instance()
4020 if (!pvt) in probe_one_instance()
4023 pvt->mc_node_id = nid; in probe_one_instance()
4024 pvt->F3 = F3; in probe_one_instance()
4026 ret = per_family_init(pvt); in probe_one_instance()
4030 ret = pvt->ops->hw_info_get(pvt); in probe_one_instance()
4035 if (!instance_has_memory(pvt)) { in probe_one_instance()
4040 if (!pvt->ops->ecc_enabled(pvt)) { in probe_one_instance()
4056 ret = init_one_instance(pvt); in probe_one_instance()
4066 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); in probe_one_instance()
4069 pvt->ops->dump_misc_regs(pvt); in probe_one_instance()
4074 hw_info_put(pvt); in probe_one_instance()
4075 kfree(pvt); in probe_one_instance()
4090 struct amd64_pvt *pvt; in remove_one_instance() local
4097 pvt = mci->pvt_info; in remove_one_instance()
4107 hw_info_put(pvt); in remove_one_instance()
4108 kfree(pvt); in remove_one_instance()