Lines Matching +full:ganged +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
10 * cleared to prevent re-enabling the hardware by this driver.
19 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
31 /* Per-node stuff */
39 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
81 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
94 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
106 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
107 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
109 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
119 * DCT0 -> F2x040..
120 * DCT1 -> F2x140..
129 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
132 return -EINVAL; in amd64_read_dct_pci_cfg()
154 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
160 return -EINVAL; in amd64_read_dct_pci_cfg()
166 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
201 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { in __set_scrub_rate()
215 if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
217 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
219 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
221 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
232 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate()
235 if (pvt->fam == 0xf) in set_scrub_rate()
238 if (pvt->fam == 0x15) { in set_scrub_rate()
240 if (pvt->model < 0x10) in set_scrub_rate()
243 if (pvt->model == 0x60) in set_scrub_rate()
251 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate()
252 int i, retval = -EINVAL; in get_scrub_rate()
255 if (pvt->fam == 0x15) { in get_scrub_rate()
257 if (pvt->model < 0x10) in get_scrub_rate()
260 if (pvt->model == 0x60) in get_scrub_rate()
261 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
263 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
265 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
287 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be in base_limit_match()
289 * Here we discard bits 63-40. See section 3.4.2 of AMD publication in base_limit_match()
290 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 in base_limit_match()
316 pvt = mci->pvt_info; in find_mc_by_sys_addr()
378 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
379 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
380 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
389 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
390 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
391 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
392 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
407 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
408 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
411 if (pvt->fam == 0x15) in get_cs_base_and_mask()
429 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
432 pvt->csels[dct].csbases[i]
435 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
438 for (i = 0; i < pvt->max_mcs; i++)
442 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
450 pvt = mci->pvt_info; in input_addr_to_csrow()
463 pvt->mc_node_id); in input_addr_to_csrow()
469 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
471 return -1; in input_addr_to_csrow()
480 * - The revision of the node is not E or greater. In this case, the DRAM Hole
483 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
487 * complete 32-bit values despite the fact that the bitfields in the DHAR
488 * only represent bits 31-24 of the base and offset values.
493 struct amd64_pvt *pvt = mci->pvt_info; in get_dram_hole_info()
496 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in get_dram_hole_info()
498 pvt->ext_model, pvt->mc_node_id); in get_dram_hole_info()
503 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in get_dram_hole_info()
510 pvt->mc_node_id); in get_dram_hole_info()
516 /* +------------------+--------------------+--------------------+----- in get_dram_hole_info()
518 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | in get_dram_hole_info()
522 * | | | (0xffffffff-x))] | in get_dram_hole_info()
523 * +------------------+--------------------+--------------------+----- in get_dram_hole_info()
533 *hole_size = (1ULL << 32) - *hole_base; in get_dram_hole_info()
535 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in get_dram_hole_info()
539 pvt->mc_node_id, (unsigned long)*hole_base, in get_dram_hole_info()
551 struct amd64_pvt *pvt = mci->pvt_info; \
553 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
602 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_show()
603 return sprintf(buf, "0x%x\n", pvt->injection.section); in inject_section_show()
607 * store error injection section value which refers to one of 4 16-byte sections
608 * within a 64-byte cacheline
617 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_store()
627 return -EINVAL; in inject_section_store()
630 pvt->injection.section = (u32) value; in inject_section_store()
638 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_show()
639 return sprintf(buf, "0x%x\n", pvt->injection.word); in inject_word_show()
643 * store error injection word value which refers to one of 9 16-bit word of the
644 * 16-byte (128-bit + ECC bits) section
653 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_store()
663 return -EINVAL; in inject_word_store()
666 pvt->injection.word = (u32) value; in inject_word_store()
675 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_show()
676 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in inject_ecc_vector_show()
689 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_store()
699 return -EINVAL; in inject_ecc_vector_store()
702 pvt->injection.bit_map = (u32) value; in inject_ecc_vector_store()
715 struct amd64_pvt *pvt = mci->pvt_info; in inject_read_store()
724 /* Form value to choose 16-byte section of cacheline */ in inject_read_store()
725 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_read_store()
727 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_read_store()
729 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); in inject_read_store()
732 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_read_store()
748 struct amd64_pvt *pvt = mci->pvt_info; in inject_write_store()
757 /* Form value to choose 16-byte section of cacheline */ in inject_write_store()
758 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_write_store()
760 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_write_store()
762 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); in inject_write_store()
771 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_write_store()
775 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); in inject_write_store()
811 struct amd64_pvt *pvt = mci->pvt_info; in inj_is_visible()
814 if (pvt->fam >= 0x10 && pvt->fam <= 0x16) in inj_is_visible()
815 return attr->mode; in inj_is_visible()
857 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr()
861 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
868 dram_addr = sys_addr - hole_offset; in sys_addr_to_dram_addr()
880 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 in sys_addr_to_dram_addr()
881 * only deals with 40-bit values. Therefore we discard bits 63-40 of in sys_addr_to_dram_addr()
884 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture in sys_addr_to_dram_addr()
887 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; in sys_addr_to_dram_addr()
916 pvt = mci->pvt_info; in dram_addr_to_input_addr()
919 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) in dram_addr_to_input_addr()
954 err->page = (u32) (error_address >> PAGE_SHIFT); in error_address_to_page_and_offset()
955 err->offset = ((u32) error_address) & ~PAGE_MASK; in error_address_to_page_and_offset()
963 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
972 if (csrow == -1) in sys_addr_to_csrow()
1006 * Mapping of nodes from hardware-provided AMD Node ID to a in gpu_get_node_map()
1010 if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3) in gpu_get_node_map()
1014 * Node ID 0 is reserved for CPUs. Therefore, a non-zero Node ID in gpu_get_node_map()
1022 ret = -ENODEV; in gpu_get_node_map()
1043 u8 nid = (m->ipid >> 44) & 0xF; in fixup_node_id()
1045 if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2) in fixup_node_id()
1052 /* Convert the hardware-provided AMD Node ID to a Linux logical one. */ in fixup_node_id()
1053 return nid - gpu_node_map.base_node_id + 1; in fixup_node_id()
1067 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in dct_determine_edac_cap()
1071 if (pvt->dclr0 & BIT(bit)) in dct_determine_edac_cap()
1083 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1089 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1105 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1106 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1109 if (pvt->fam == 0xf) { in dct_debug_display_dimm_sizes()
1111 if (pvt->ext_model < K8_REV_F) in dct_debug_display_dimm_sizes()
1117 if (pvt->fam == 0x10) { in dct_debug_display_dimm_sizes()
1118 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in dct_debug_display_dimm_sizes()
1119 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1121 pvt->csels[1].csbases : in dct_debug_display_dimm_sizes()
1122 pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1124 dbam = pvt->dbam0; in dct_debug_display_dimm_sizes()
1125 dcsb = pvt->csels[1].csbases; in dct_debug_display_dimm_sizes()
1142 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1148 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1163 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1164 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
1180 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
1181 edac_dbg(1, " DCT 128bit mode width: %s\n", in debug_dump_dramcfg_low()
1211 /* Asymmetric dual-rank DIMM support. */ in umc_get_cs_mode()
1224 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { in umc_get_cs_mode()
1250 msb = fls(addr_mask_orig) - 1; in __addr_mask_to_cs_size()
1252 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); in __addr_mask_to_cs_size()
1255 addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); in __addr_mask_to_cs_size()
1291 * CS0 and CS1 -> MASK0 / DIMM0 in umc_addr_mask_to_cs_size()
1292 * CS2 and CS3 -> MASK1 / DIMM1 in umc_addr_mask_to_cs_size()
1297 * CS0 -> MASK0 -> DIMM0 in umc_addr_mask_to_cs_size()
1298 * CS1 -> MASK1 -> DIMM0 in umc_addr_mask_to_cs_size()
1299 * CS2 -> MASK2 -> DIMM1 in umc_addr_mask_to_cs_size()
1300 * CS3 -> MASK3 -> DIMM1 in umc_addr_mask_to_cs_size()
1307 if (!pvt->flags.zn_regs_v2) in umc_addr_mask_to_cs_size()
1310 /* Asymmetric dual-rank DIMM support. */ in umc_addr_mask_to_cs_size()
1312 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1314 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1346 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1348 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in umc_dump_misc_regs()
1349 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in umc_dump_misc_regs()
1350 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in umc_dump_misc_regs()
1351 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in umc_dump_misc_regs()
1352 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); in umc_dump_misc_regs()
1355 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", in umc_dump_misc_regs()
1356 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); in umc_dump_misc_regs()
1358 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); in umc_dump_misc_regs()
1360 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); in umc_dump_misc_regs()
1362 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); in umc_dump_misc_regs()
1370 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in dct_dump_misc_regs()
1373 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in dct_dump_misc_regs()
1376 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in dct_dump_misc_regs()
1377 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in dct_dump_misc_regs()
1379 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in dct_dump_misc_regs()
1381 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in dct_dump_misc_regs()
1384 pvt->dhar, dhar_base(pvt), in dct_dump_misc_regs()
1385 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in dct_dump_misc_regs()
1391 if (pvt->fam == 0xf) in dct_dump_misc_regs()
1396 /* Only if NOT ganged does dclr1 have valid info */ in dct_dump_misc_regs()
1398 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in dct_dump_misc_regs()
1402 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dct_dump_misc_regs()
1410 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in dct_prep_chip_selects()
1411 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1412 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in dct_prep_chip_selects()
1413 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in dct_prep_chip_selects()
1414 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in dct_prep_chip_selects()
1415 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in dct_prep_chip_selects()
1417 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1418 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in dct_prep_chip_selects()
1427 pvt->csels[umc].b_cnt = 4; in umc_prep_chip_selects()
1428 pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2; in umc_prep_chip_selects()
1448 base = &pvt->csels[umc].csbases[cs]; in umc_read_base_mask()
1449 base_sec = &pvt->csels[umc].csbases_sec[cs]; in umc_read_base_mask()
1454 if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) { in umc_read_base_mask()
1460 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) { in umc_read_base_mask()
1471 mask = &pvt->csels[umc].csmasks[cs]; in umc_read_base_mask()
1472 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in umc_read_base_mask()
1477 if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) { in umc_read_base_mask()
1483 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) { in umc_read_base_mask()
1502 u32 *base0 = &pvt->csels[0].csbases[cs]; in dct_read_base_mask()
1503 u32 *base1 = &pvt->csels[1].csbases[cs]; in dct_read_base_mask()
1509 if (pvt->fam == 0xf) in dct_read_base_mask()
1514 cs, *base1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1521 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in dct_read_base_mask()
1522 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in dct_read_base_mask()
1528 if (pvt->fam == 0xf) in dct_read_base_mask()
1533 cs, *mask1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1544 umc = &pvt->umc[i]; in umc_determine_memory_type()
1546 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) { in umc_determine_memory_type()
1547 umc->dram_type = MEM_EMPTY; in umc_determine_memory_type()
1555 if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { in umc_determine_memory_type()
1556 if (umc->dimm_cfg & BIT(5)) in umc_determine_memory_type()
1557 umc->dram_type = MEM_LRDDR5; in umc_determine_memory_type()
1558 else if (umc->dimm_cfg & BIT(4)) in umc_determine_memory_type()
1559 umc->dram_type = MEM_RDDR5; in umc_determine_memory_type()
1561 umc->dram_type = MEM_DDR5; in umc_determine_memory_type()
1563 if (umc->dimm_cfg & BIT(5)) in umc_determine_memory_type()
1564 umc->dram_type = MEM_LRDDR4; in umc_determine_memory_type()
1565 else if (umc->dimm_cfg & BIT(4)) in umc_determine_memory_type()
1566 umc->dram_type = MEM_RDDR4; in umc_determine_memory_type()
1568 umc->dram_type = MEM_DDR4; in umc_determine_memory_type()
1571 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); in umc_determine_memory_type()
1579 switch (pvt->fam) { in dct_determine_memory_type()
1581 if (pvt->ext_model >= K8_REV_F) in dct_determine_memory_type()
1584 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in dct_determine_memory_type()
1588 if (pvt->dchr0 & DDR3_MODE) in dct_determine_memory_type()
1591 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in dct_determine_memory_type()
1595 if (pvt->model < 0x60) in dct_determine_memory_type()
1608 dcsm = pvt->csels[0].csmasks[0]; in dct_determine_memory_type()
1611 pvt->dram_type = MEM_DDR4; in dct_determine_memory_type()
1612 else if (pvt->dclr0 & BIT(16)) in dct_determine_memory_type()
1613 pvt->dram_type = MEM_DDR3; in dct_determine_memory_type()
1615 pvt->dram_type = MEM_LRDDR3; in dct_determine_memory_type()
1617 pvt->dram_type = MEM_RDDR3; in dct_determine_memory_type()
1625 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in dct_determine_memory_type()
1626 pvt->dram_type = MEM_EMPTY; in dct_determine_memory_type()
1629 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in dct_determine_memory_type()
1633 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in dct_determine_memory_type()
1639 u16 mce_nid = topology_amd_node_id(m->extcpu); in get_error_address()
1649 pvt = mci->pvt_info; in get_error_address()
1651 if (pvt->fam == 0xf) { in get_error_address()
1656 addr = m->addr & GENMASK_ULL(end_bit, start_bit); in get_error_address()
1661 if (pvt->fam == 0x15) { in get_error_address()
1670 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1685 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1709 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) && in pci_get_related_function()
1710 (dev->bus->number == related->bus->number) && in pci_get_related_function()
1711 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) in pci_get_related_function()
1726 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1727 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1729 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1735 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1736 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1739 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1746 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1748 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1753 f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc); in read_dram_base_limit_regs()
1759 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1762 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1764 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1767 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1775 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow()
1783 err->src_mci = find_mc_by_sys_addr(mci, sys_addr); in k8_map_sysaddr_to_csrow()
1784 if (!err->src_mci) { in k8_map_sysaddr_to_csrow()
1787 err->err_code = ERR_NODE; in k8_map_sysaddr_to_csrow()
1792 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); in k8_map_sysaddr_to_csrow()
1793 if (err->csrow < 0) { in k8_map_sysaddr_to_csrow()
1794 err->err_code = ERR_CSROW; in k8_map_sysaddr_to_csrow()
1799 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1800 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in k8_map_sysaddr_to_csrow()
1801 if (err->channel < 0) { in k8_map_sysaddr_to_csrow()
1807 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " in k8_map_sysaddr_to_csrow()
1809 err->syndrome); in k8_map_sysaddr_to_csrow()
1810 err->err_code = ERR_CHANNEL; in k8_map_sysaddr_to_csrow()
1815 * non-chipkill ecc mode in k8_map_sysaddr_to_csrow()
1818 * channel number when using non-chipkill memory. This method in k8_map_sysaddr_to_csrow()
1820 * (Wish the email was placed in this comment - norsk) in k8_map_sysaddr_to_csrow()
1822 err->channel = ((sys_addr & BIT(3)) != 0); in k8_map_sysaddr_to_csrow()
1843 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1845 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1849 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1879 return 32 << (cs_mode - diff); in k8_dbam_to_chip_select()
1893 cs_size = -1; in ddr3_cs_size()
1903 if (cs_size != -1) in ddr3_cs_size()
1915 cs_size = -1; in ddr3_lrdimm_cs_size()
1923 if (cs_size != -1) in ddr3_lrdimm_cs_size()
1934 cs_size = -1; in ddr4_cs_size()
1947 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1951 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1973 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1977 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1979 return -1; in f15_m60h_dbam_to_chip_select()
1982 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1991 return -1; in f15_m60h_dbam_to_chip_select()
2009 return -1; in f16_dbam_to_chip_select()
2017 if (pvt->fam == 0xf) in read_dram_ctl_register()
2020 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
2022 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
2024 edac_dbg(0, " DCTs operate in %s mode\n", in read_dram_ctl_register()
2025 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
2041 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
2045 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
2076 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
2082 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
2091 * see F2x110[DctSelIntLvAddr] - channel interleave mode in f1x_determine_channel()
2130 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
2167 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); in f1x_get_norm_dct_addr()
2196 * -EINVAL: NOT FOUND
2197 * 0..csrow = Chip-Select Row
2204 int cs_found = -EINVAL; in f1x_lookup_addr_in_dct()
2211 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
2230 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
2244 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
2252 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
2254 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
2258 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
2281 int cs_found = -EINVAL; in f1x_match_to_this_node()
2299 return -EINVAL; in f1x_match_to_this_node()
2303 return -EINVAL; in f1x_match_to_this_node()
2361 int cs_found = -EINVAL; in f15_m30h_match_to_this_node()
2373 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2374 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2384 return -EINVAL; in f15_m30h_match_to_this_node()
2391 return -EINVAL; in f15_m30h_match_to_this_node()
2401 return -EINVAL; in f15_m30h_match_to_this_node()
2407 return -EINVAL; in f15_m30h_match_to_this_node()
2409 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2417 return -EINVAL; in f15_m30h_match_to_this_node()
2427 chan_addr = sys_addr - chan_offset; in f15_m30h_match_to_this_node()
2438 return -EINVAL; in f15_m30h_match_to_this_node()
2448 return -EINVAL; in f15_m30h_match_to_this_node()
2452 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2467 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2484 int cs_found = -EINVAL; in f1x_translate_sysaddr_to_cs()
2491 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2517 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow()
2521 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2522 if (err->csrow < 0) { in f1x_map_sysaddr_to_csrow()
2523 err->err_code = ERR_CSROW; in f1x_map_sysaddr_to_csrow()
2529 * ganged. Otherwise @chan should already contain the channel at in f1x_map_sysaddr_to_csrow()
2533 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in f1x_map_sysaddr_to_csrow()
2637 return -1; in decode_syndrome()
2660 return -1; in map_err_sym_to_channel()
2668 return -1; in map_err_sym_to_channel()
2673 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome()
2674 int err_sym = -1; in get_channel_from_ecc_syndrome()
2676 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2679 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2680 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2683 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2685 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2689 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2709 switch (err->err_code) { in __log_ecc_error()
2720 string = "Unknown syndrome - possible error reporting race"; in __log_ecc_error()
2723 string = "MCA_SYND not valid - unknown syndrome and csrow"; in __log_ecc_error()
2734 err->page, err->offset, err->syndrome, in __log_ecc_error()
2735 err->csrow, err->channel, -1, in __log_ecc_error()
2743 u8 ecc_type = (m->status >> 45) & 0x3; in decode_bus_error()
2744 u8 xec = XEC(m->status, 0x1f); in decode_bus_error()
2745 u16 ec = EC(m->status); in decode_bus_error()
2753 pvt = mci->pvt_info; in decode_bus_error()
2768 err.syndrome = extract_syndrome(m->status); in decode_bus_error()
2770 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2789 err->channel = (m->ipid & GENMASK(31, 0)) >> 20; in umc_get_err_info()
2790 err->csrow = m->synd & 0x7; in umc_get_err_info()
2795 u8 ecc_type = (m->status >> 45) & 0x3; in decode_umc_error()
2808 pvt = mci->pvt_info; in decode_umc_error()
2812 if (m->status & MCI_STATUS_DEFERRED) in decode_umc_error()
2815 if (!(m->status & MCI_STATUS_SYNDV)) { in decode_umc_error()
2821 u8 length = (m->synd >> 18) & 0x3f; in decode_umc_error()
2824 err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0); in decode_umc_error()
2829 pvt->ops->get_err_info(m, &err); in decode_umc_error()
2831 a_err.addr = m->addr; in decode_umc_error()
2832 a_err.ipid = m->ipid; in decode_umc_error()
2833 a_err.cpu = m->extcpu; in decode_umc_error()
2848 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2855 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2856 if (!pvt->F1) { in reserve_mc_sibling_devs()
2858 return -ENODEV; in reserve_mc_sibling_devs()
2862 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2863 if (!pvt->F2) { in reserve_mc_sibling_devs()
2864 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2865 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2868 return -ENODEV; in reserve_mc_sibling_devs()
2872 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2874 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2875 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2876 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2883 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2885 if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2888 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2890 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2891 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2894 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2895 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2904 u8 nid = pvt->mc_node_id; in umc_read_mc_regs()
2912 umc = &pvt->umc[i]; in umc_read_mc_regs()
2915 umc->dimm_cfg = tmp; in umc_read_mc_regs()
2918 umc->umc_cfg = tmp; in umc_read_mc_regs()
2921 umc->sdp_ctrl = tmp; in umc_read_mc_regs()
2924 umc->ecc_ctrl = tmp; in umc_read_mc_regs()
2927 umc->umc_cap_hi = tmp; in umc_read_mc_regs()
2942 * those are Read-As-Zero. in dct_read_mc_regs()
2944 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in dct_read_mc_regs()
2945 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in dct_read_mc_regs()
2950 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in dct_read_mc_regs()
2951 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in dct_read_mc_regs()
2956 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in dct_read_mc_regs()
2977 (rw & 0x1) ? "R" : "-", in dct_read_mc_regs()
2978 (rw & 0x2) ? "W" : "-", in dct_read_mc_regs()
2983 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in dct_read_mc_regs()
2984 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in dct_read_mc_regs()
2986 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in dct_read_mc_regs()
2988 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in dct_read_mc_regs()
2989 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in dct_read_mc_regs()
2992 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in dct_read_mc_regs()
2993 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in dct_read_mc_regs()
3003 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
3004 * k8 private pointer to -->
3012 * 0-3 CSROWs 0 and 1
3013 * 4-7 CSROWs 2 and 3
3014 * 8-11 CSROWs 4 and 5
3015 * 12-15 CSROWs 6 and 7
3018 * The meaning of the values depends on CPU revision and dual-channel state,
3023 * single channel or two (2) DIMMs in dual channel mode.
3035 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in dct_get_csrow_nr_pages()
3041 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3042 nr_pages <<= 20 - PAGE_SHIFT; in dct_get_csrow_nr_pages()
3059 nr_pages <<= 20 - PAGE_SHIFT; in umc_get_csrow_nr_pages()
3070 struct amd64_pvt *pvt = mci->pvt_info; in umc_init_csrows()
3076 if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) { in umc_init_csrows()
3079 } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) { in umc_init_csrows()
3082 } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) { in umc_init_csrows()
3085 } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) { in umc_init_csrows()
3094 dimm = mci->csrows[cs]->channels[umc]->dimm; in umc_init_csrows()
3097 pvt->mc_node_id, cs); in umc_init_csrows()
3099 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs); in umc_init_csrows()
3100 dimm->mtype = pvt->umc[umc].dram_type; in umc_init_csrows()
3101 dimm->edac_mode = edac_mode; in umc_init_csrows()
3102 dimm->dtype = dev_type; in umc_init_csrows()
3103 dimm->grain = 64; in umc_init_csrows()
3114 struct amd64_pvt *pvt = mci->pvt_info; in dct_init_csrows()
3122 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in dct_init_csrows()
3124 pvt->nbcfg = val; in dct_init_csrows()
3127 pvt->mc_node_id, val, in dct_init_csrows()
3137 if (pvt->fam != 0xf) in dct_init_csrows()
3143 csrow = mci->csrows[i]; in dct_init_csrows()
3146 pvt->mc_node_id, i); in dct_init_csrows()
3150 csrow->channels[0]->dimm->nr_pages = nr_pages; in dct_init_csrows()
3154 if (pvt->fam != 0xf && row_dct1) { in dct_init_csrows()
3157 csrow->channels[1]->dimm->nr_pages = row_dct1_pages; in dct_init_csrows()
3163 /* Determine DIMM ECC mode: */ in dct_init_csrows()
3164 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in dct_init_csrows()
3165 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in dct_init_csrows()
3170 for (j = 0; j < pvt->max_mcs; j++) { in dct_init_csrows()
3171 dimm = csrow->channels[j]->dimm; in dct_init_csrows()
3172 dimm->mtype = pvt->dram_type; in dct_init_csrows()
3173 dimm->edac_mode = edac_mode; in dct_init_csrows()
3174 dimm->grain = 64; in dct_init_csrows()
3207 nbe = reg->l & MSR_MCGCTL_NBE; in nb_mce_bank_enabled_on_node()
3210 cpu, reg->q, in nb_mce_bank_enabled_on_node()
3230 return -ENOMEM; in toggle_ecc_err_reporting()
3242 if (reg->l & MSR_MCGCTL_NBE) in toggle_ecc_err_reporting()
3243 s->flags.nb_mce_enable = 1; in toggle_ecc_err_reporting()
3245 reg->l |= MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3250 if (!s->flags.nb_mce_enable) in toggle_ecc_err_reporting()
3251 reg->l &= ~MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3274 s->old_nbctl = value & mask; in enable_ecc_error_reporting()
3275 s->nbctl_valid = true; in enable_ecc_error_reporting()
3288 s->flags.nb_ecc_prev = 0; in enable_ecc_error_reporting()
3304 s->flags.nb_ecc_prev = 1; in enable_ecc_error_reporting()
3318 if (!s->nbctl_valid) in restore_ecc_error_reporting()
3323 value |= s->old_nbctl; in restore_ecc_error_reporting()
3327 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ in restore_ecc_error_reporting()
3328 if (!s->flags.nb_ecc_prev) { in restore_ecc_error_reporting()
3341 u16 nid = pvt->mc_node_id; in dct_ecc_enabled()
3346 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in dct_ecc_enabled()
3366 u16 nid = pvt->mc_node_id; in umc_ecc_enabled()
3371 umc = &pvt->umc[i]; in umc_ecc_enabled()
3374 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) in umc_ecc_enabled()
3379 if (umc->umc_cap_hi & UMC_ECC_ENABLED) in umc_ecc_enabled()
3403 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in umc_determine_edac_ctl_cap()
3404 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in umc_determine_edac_ctl_cap()
3405 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in umc_determine_edac_ctl_cap()
3407 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in umc_determine_edac_ctl_cap()
3408 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in umc_determine_edac_ctl_cap()
3414 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in umc_determine_edac_ctl_cap()
3420 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in umc_determine_edac_ctl_cap()
3422 mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED; in umc_determine_edac_ctl_cap()
3424 mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED; in umc_determine_edac_ctl_cap()
3430 struct amd64_pvt *pvt = mci->pvt_info; in dct_setup_mci_misc_attrs()
3432 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; in dct_setup_mci_misc_attrs()
3433 mci->edac_ctl_cap = EDAC_FLAG_NONE; in dct_setup_mci_misc_attrs()
3435 if (pvt->nbcap & NBCAP_SECDED) in dct_setup_mci_misc_attrs()
3436 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in dct_setup_mci_misc_attrs()
3438 if (pvt->nbcap & NBCAP_CHIPKILL) in dct_setup_mci_misc_attrs()
3439 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in dct_setup_mci_misc_attrs()
3441 mci->edac_cap = dct_determine_edac_cap(pvt); in dct_setup_mci_misc_attrs()
3442 mci->mod_name = EDAC_MOD_STR; in dct_setup_mci_misc_attrs()
3443 mci->ctl_name = pvt->ctl_name; in dct_setup_mci_misc_attrs()
3444 mci->dev_name = pci_name(pvt->F3); in dct_setup_mci_misc_attrs()
3445 mci->ctl_page_to_phys = NULL; in dct_setup_mci_misc_attrs()
3448 mci->set_sdram_scrub_rate = set_scrub_rate; in dct_setup_mci_misc_attrs()
3449 mci->get_sdram_scrub_rate = get_scrub_rate; in dct_setup_mci_misc_attrs()
3456 struct amd64_pvt *pvt = mci->pvt_info; in umc_setup_mci_misc_attrs()
3458 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4; in umc_setup_mci_misc_attrs()
3459 mci->edac_ctl_cap = EDAC_FLAG_NONE; in umc_setup_mci_misc_attrs()
3463 mci->edac_cap = umc_determine_edac_cap(pvt); in umc_setup_mci_misc_attrs()
3464 mci->mod_name = EDAC_MOD_STR; in umc_setup_mci_misc_attrs()
3465 mci->ctl_name = pvt->ctl_name; in umc_setup_mci_misc_attrs()
3466 mci->dev_name = pci_name(pvt->F3); in umc_setup_mci_misc_attrs()
3467 mci->ctl_page_to_phys = NULL; in umc_setup_mci_misc_attrs()
3474 int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id); in dct_hw_info_get()
3489 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in umc_hw_info_get()
3490 if (!pvt->umc) in umc_hw_info_get()
3491 return -ENOMEM; in umc_hw_info_get()
3520 u8 ch = (m->ipid & GENMASK(31, 0)) >> 20; in gpu_get_err_info()
3521 u8 phy = ((m->ipid >> 12) & 0xf); in gpu_get_err_info()
3523 err->channel = ch % 2 ? phy + 4 : phy; in gpu_get_err_info()
3524 err->csrow = phy; in gpu_get_err_info()
3530 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; in gpu_addr_mask_to_cs_size()
3555 umc = &pvt->umc[i]; in gpu_dump_misc_regs()
3557 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in gpu_dump_misc_regs()
3558 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in gpu_dump_misc_regs()
3559 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in gpu_dump_misc_regs()
3572 nr_pages <<= 20 - PAGE_SHIFT; in gpu_get_csrow_nr_pages()
3582 struct amd64_pvt *pvt = mci->pvt_info; in gpu_init_csrows()
3591 dimm = mci->csrows[umc]->channels[cs]->dimm; in gpu_init_csrows()
3594 pvt->mc_node_id, cs); in gpu_init_csrows()
3596 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs); in gpu_init_csrows()
3597 dimm->edac_mode = EDAC_SECDED; in gpu_init_csrows()
3598 dimm->mtype = pvt->dram_type; in gpu_init_csrows()
3599 dimm->dtype = DEV_X16; in gpu_init_csrows()
3600 dimm->grain = 64; in gpu_init_csrows()
3607 struct amd64_pvt *pvt = mci->pvt_info; in gpu_setup_mci_misc_attrs()
3609 mci->mtype_cap = MEM_FLAG_HBM2; in gpu_setup_mci_misc_attrs()
3610 mci->edac_ctl_cap = EDAC_FLAG_SECDED; in gpu_setup_mci_misc_attrs()
3612 mci->edac_cap = EDAC_FLAG_EC; in gpu_setup_mci_misc_attrs()
3613 mci->mod_name = EDAC_MOD_STR; in gpu_setup_mci_misc_attrs()
3614 mci->ctl_name = pvt->ctl_name; in gpu_setup_mci_misc_attrs()
3615 mci->dev_name = pci_name(pvt->F3); in gpu_setup_mci_misc_attrs()
3616 mci->ctl_page_to_phys = NULL; in gpu_setup_mci_misc_attrs()
3649 return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12); in gpu_get_umc_base()
3654 u8 nid = pvt->mc_node_id; in gpu_read_mc_regs()
3661 umc = &pvt->umc[i]; in gpu_read_mc_regs()
3664 umc->umc_cfg = tmp; in gpu_read_mc_regs()
3667 umc->sdp_ctrl = tmp; in gpu_read_mc_regs()
3670 umc->ecc_ctrl = tmp; in gpu_read_mc_regs()
3683 base = &pvt->csels[umc].csbases[cs]; in gpu_read_base_mask()
3685 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) { in gpu_read_base_mask()
3691 mask = &pvt->csels[umc].csmasks[cs]; in gpu_read_base_mask()
3693 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) { in gpu_read_base_mask()
3706 pvt->csels[umc].b_cnt = 8; in gpu_prep_chip_selects()
3707 pvt->csels[umc].m_cnt = 8; in gpu_prep_chip_selects()
3719 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in gpu_hw_info_get()
3720 if (!pvt->umc) in gpu_hw_info_get()
3721 return -ENOMEM; in gpu_hw_info_get()
3732 pci_dev_put(pvt->F1); in hw_info_put()
3733 pci_dev_put(pvt->F2); in hw_info_put()
3734 kfree(pvt->umc); in hw_info_put()
3765 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3766 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3767 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3768 pvt->fam = boot_cpu_data.x86; in per_family_init()
3769 pvt->max_mcs = 2; in per_family_init()
3775 if (pvt->fam >= 0x17) in per_family_init()
3776 pvt->ops = &umc_ops; in per_family_init()
3778 pvt->ops = &dct_ops; in per_family_init()
3780 switch (pvt->fam) { in per_family_init()
3782 pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ? in per_family_init()
3784 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; in per_family_init()
3785 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; in per_family_init()
3786 pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; in per_family_init()
3787 pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; in per_family_init()
3791 pvt->ctl_name = "F10h"; in per_family_init()
3792 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; in per_family_init()
3793 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; in per_family_init()
3794 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; in per_family_init()
3798 switch (pvt->model) { in per_family_init()
3800 pvt->ctl_name = "F15h_M30h"; in per_family_init()
3801 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; in per_family_init()
3802 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; in per_family_init()
3805 pvt->ctl_name = "F15h_M60h"; in per_family_init()
3806 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; in per_family_init()
3807 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; in per_family_init()
3808 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; in per_family_init()
3812 return -ENODEV; in per_family_init()
3814 pvt->ctl_name = "F15h"; in per_family_init()
3815 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; in per_family_init()
3816 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; in per_family_init()
3817 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; in per_family_init()
3823 switch (pvt->model) { in per_family_init()
3825 pvt->ctl_name = "F16h_M30h"; in per_family_init()
3826 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; in per_family_init()
3827 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; in per_family_init()
3830 pvt->ctl_name = "F16h"; in per_family_init()
3831 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; in per_family_init()
3832 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; in per_family_init()
3838 switch (pvt->model) { in per_family_init()
3840 pvt->ctl_name = "F17h_M10h"; in per_family_init()
3843 pvt->ctl_name = "F17h_M30h"; in per_family_init()
3844 pvt->max_mcs = 8; in per_family_init()
3847 pvt->ctl_name = "F17h_M60h"; in per_family_init()
3850 pvt->ctl_name = "F17h_M70h"; in per_family_init()
3853 pvt->ctl_name = "F17h"; in per_family_init()
3859 pvt->ctl_name = "F18h"; in per_family_init()
3863 switch (pvt->model) { in per_family_init()
3865 pvt->ctl_name = "F19h"; in per_family_init()
3866 pvt->max_mcs = 8; in per_family_init()
3869 pvt->ctl_name = "F19h_M10h"; in per_family_init()
3870 pvt->max_mcs = 12; in per_family_init()
3871 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3874 pvt->ctl_name = "F19h_M20h"; in per_family_init()
3877 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) { in per_family_init()
3878 pvt->ctl_name = "MI200"; in per_family_init()
3879 pvt->max_mcs = 4; in per_family_init()
3880 pvt->dram_type = MEM_HBM2; in per_family_init()
3881 pvt->gpu_umc_base = 0x50000; in per_family_init()
3882 pvt->ops = &gpu_ops; in per_family_init()
3884 pvt->ctl_name = "F19h_M30h"; in per_family_init()
3885 pvt->max_mcs = 8; in per_family_init()
3889 pvt->ctl_name = "F19h_M50h"; in per_family_init()
3892 pvt->ctl_name = "F19h_M60h"; in per_family_init()
3893 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3896 pvt->ctl_name = "F19h_M70h"; in per_family_init()
3897 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3900 pvt->ctl_name = "F19h_M90h"; in per_family_init()
3901 pvt->max_mcs = 4; in per_family_init()
3902 pvt->dram_type = MEM_HBM3; in per_family_init()
3903 pvt->gpu_umc_base = 0x90000; in per_family_init()
3904 pvt->ops = &gpu_ops; in per_family_init()
3907 pvt->ctl_name = "F19h_MA0h"; in per_family_init()
3908 pvt->max_mcs = 12; in per_family_init()
3909 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3915 switch (pvt->model) { in per_family_init()
3917 pvt->ctl_name = "F1Ah"; in per_family_init()
3918 pvt->max_mcs = 12; in per_family_init()
3919 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3922 pvt->ctl_name = "F1Ah_M40h"; in per_family_init()
3923 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3930 return -ENODEV; in per_family_init()
3950 bool is_gpu = (pvt->ops == &gpu_ops); in get_layer_size()
3953 return is_gpu ? pvt->max_mcs in get_layer_size()
3954 : pvt->csels[0].b_cnt; in get_layer_size()
3956 return is_gpu ? pvt->csels[0].b_cnt in get_layer_size()
3957 : pvt->max_mcs; in get_layer_size()
3964 int ret = -ENOMEM; in init_one_instance()
3973 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3977 mci->pvt_info = pvt; in init_one_instance()
3978 mci->pdev = &pvt->F3->dev; in init_one_instance()
3980 pvt->ops->setup_mci_misc_attrs(mci); in init_one_instance()
3982 ret = -ENODEV; in init_one_instance()
3997 for (dct = 0; dct < pvt->max_mcs; dct++) { in instance_has_memory()
4007 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in probe_one_instance()
4012 ret = -ENOMEM; in probe_one_instance()
4023 pvt->mc_node_id = nid; in probe_one_instance()
4024 pvt->F3 = F3; in probe_one_instance()
4030 ret = pvt->ops->hw_info_get(pvt); in probe_one_instance()
4040 if (!pvt->ops->ecc_enabled(pvt)) { in probe_one_instance()
4041 ret = -ENODEV; in probe_one_instance()
4066 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); in probe_one_instance()
4069 pvt->ops->dump_misc_regs(pvt); in probe_one_instance()
4087 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in remove_one_instance()
4093 mci = edac_mc_del_mc(&F3->dev); in remove_one_instance()
4097 pvt = mci->pvt_info; in remove_one_instance()
4105 mci->pvt_info = NULL; in remove_one_instance()
4140 int err = -ENODEV; in amd64_edac_init()
4144 return -EBUSY; in amd64_edac_init()
4148 return -EBUSY; in amd64_edac_init()
4151 return -ENODEV; in amd64_edac_init()
4154 return -ENODEV; in amd64_edac_init()
4158 err = -ENOMEM; in amd64_edac_init()
4171 while (--i >= 0) in amd64_edac_init()
4179 err = -ENODEV; in amd64_edac_init()
4192 amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR); in amd64_edac_init()