Lines Matching full:dct
100 * Select DCT to which PCI cfg accesses are routed
102 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
108 reg |= dct; in f15h_select_dct()
114 * Depending on the family, F2 DCT reads need special handling:
116 * K8: has a single DCT only and no address offsets >= 0x100
118 * F10h: each DCT has its own set of regs
122 * F16h: has only 1 DCT
124 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
126 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
131 if (dct || offset >= 0x100) in amd64_read_dct_pci_cfg()
136 if (dct) { in amd64_read_dct_pci_cfg()
152 * We should select which DCT we access using F1x10C[DctCfgSel] in amd64_read_dct_pci_cfg()
154 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
155 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
159 if (dct) in amd64_read_dct_pci_cfg()
369 * compute the CS base address of the @csrow on the DRAM controller @dct.
372 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
379 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
380 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
391 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
392 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
407 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
408 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
428 #define for_each_chip_select(i, dct, pvt) \ argument
429 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
431 #define chip_select_base(i, dct, pvt) \ argument
432 pvt->csels[dct].csbases[i]
434 #define for_each_chip_select_mask(i, dct, pvt) \ argument
435 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
1130 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); in dct_debug_display_dimm_sizes()
1166 * It's assumed all LRDIMMs in a DCT are going to be of in debug_dump_dramcfg_low()
1181 edac_dbg(1, " DCT 128bit mode width: %s\n", in debug_dump_dramcfg_low()
1603 * 'Rank' value on a DCT. But this is not the common case. So, in dct_determine_memory_type()
1840 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1843 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1944 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1947 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1958 * F15h supports only 64bit DCT interfaces
1960 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1969 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1973 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
2002 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
2028 edac_dbg(0, " Address range split per DCT: %s\n", in read_dram_ctl_register()
2045 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
2076 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
2096 /* return DCT select function: 0=DCT0, 1=DCT1 */ in f1x_determine_channel()
2122 /* Convert the sys_addr to the normalized DCT address */
2137 * DRAM address space on this DCT is hoisted above 4Gb && in f1x_get_norm_dct_addr()
2159 * remove dram base to normalize to DCT address in f1x_get_norm_dct_addr()
2174 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
2178 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
2179 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
2181 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
2182 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
2192 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
2199 static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct) in f1x_lookup_addr_in_dct() argument
2213 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct); in f1x_lookup_addr_in_dct()
2215 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
2216 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
2219 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2234 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
2348 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); in f1x_match_to_this_node()
2394 /* Verify sys_addr is within DCT Range. */ in f15_m30h_match_to_this_node()
2403 /* Verify number of dct's that participate in channel interleaving. */ in f15_m30h_match_to_this_node()
2421 /* Get normalized DCT addr */ in f15_m30h_match_to_this_node()
2460 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); in f15_m30h_match_to_this_node()
2465 * there is support for 4 DCT's, but only 2 are currently functional. in f15_m30h_match_to_this_node()
2509 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
2849 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
2861 /* Reserve the DCT Device */ in reserve_mc_sibling_devs()
3033 static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in dct_get_csrow_nr_pages() argument
3035 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in dct_get_csrow_nr_pages()
3041 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3045 csrow_nr, dct, cs_mode); in dct_get_csrow_nr_pages()
3051 static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in umc_get_csrow_nr_pages() argument
3056 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt); in umc_get_csrow_nr_pages()
3058 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in umc_get_csrow_nr_pages()
3062 csrow_nr_orig, dct, cs_mode); in umc_get_csrow_nr_pages()
3153 /* K8 has only one DCT */ in dct_init_csrows()
3179 /* get all cores on this DCT */
3566 static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in gpu_get_csrow_nr_pages() argument
3571 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in gpu_get_csrow_nr_pages()
3574 edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct); in gpu_get_csrow_nr_pages()
3995 int cs = 0, dct = 0; in instance_has_memory() local
3997 for (dct = 0; dct < pvt->max_mcs; dct++) { in instance_has_memory()
3998 for_each_chip_select(cs, dct, pvt) in instance_has_memory()
3999 cs_enabled |= csrow_enabled(cs, dct, pvt); in instance_has_memory()