Kconfig - OpenGrok cross reference for /linux-6.12.1/drivers/edac/Kconfig

13 	tristate "EDAC (Error Detection And Correction) reporting"
16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
60 	  Not all machines support hardware-driven error report. Some of those
61 	  provide a BIOS-driven error report mechanism via ACPI, using the
62 	  APEI/GHES driver. By enabling this option, the error reports provided
65 	  When this option is enabled, it will disable the hardware-driven
69 	  It should be noticed that keeping both GHES and a hardware-driven
70 	  error mechanism won't work well, as BIOS will race with OS, while
71 	  reading the error registers. So, if you want to not use "Firmware
72 	  first" GHES error mechanism, you should disable GHES either at
83 	  Support for error detection and correction of DRAM ECC errors on
86 	  When EDAC_DEBUG is enabled, hardware error injection facilities
90 	  Error Injection into the ECC detection circuits. The amd64_edac
97 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
98 	  - inject_word (0..8, 16-bit word of 16-byte section),
99 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
108 	  Support for error detection and correction for Amazon's Annapurna
109 	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.
115 	  Support for error detection and correction on the AMD 76x
122 	  Support for error detection and correction on the Intel
129 	  Support for error detection and correction on the Intel
137 	  Support for error detection and correction on the Intel
144 	  Support for error detection and correction on the Intel
151 	  Support for error detection and correction on the Intel
158 	  Support for error detection and correction on the Intel
165 	  Support for error detection and correction on the Intel
172 	  Support for error detection and correction on the Intel
173 	  E3-1200 based DRAM controllers.
179 	  Support for error detection and correction on the Intel
186 	  Support for error detection and correction the Intel
193 	  Support for error detection and correction the Intel
202 	  Support for error detection and correction on the Intel
209 	  Support for error detection and correction on the Radisys
217 	  Support for error detection and correction the Intel
224 	  Support for error detection and correction the Intel
231 	  Support for error detection and correction the Intel
235 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
238 	  Support for error detection and correction the Intel
248 	  Support for error detection and correction the Intel
250 	  system has non-volatile DIMMs you should also manually
260 	  Support for error detection and correction the Intel
262 	  system has non-volatile DIMMs you should also manually
270 	  Support for error detection and correction on the Intel
273 	  micro-server but may appear on others in the future.
280 	  Support for error detection and correction on the Intel
281 	  client SoC Integrated Memory Controller using In-Band ECC IP.
282 	  This In-Band ECC is first used on the Elkhart Lake SoC but
289 	  Support for error detection and correction on the Freescale
296 	  Support for error detection and correction on Freescale memory
303 	  Support for error detection and correction on PA Semi
310 	  Support for error detection and correction on the
315 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
318 	  Support for error detection and correction on the
319 	  AMD8131 HyperTransport PCI-X Tunnel chip.
327 	  Support for error detection and correction on the
336 	  Support for error detection and correction on the
345 	  Support for error detection and correction on the
352 	  Support for error detection and correction on the
359 	  Support for error detection and correction on the primary caches of
366 	  Support for error detection and correction on the
373 	  Support for error detection and correction on the
380 	  Support for error detection and correction on the
388 	  Support for error detection and correction on the
397 	  Support for error detection and correction on the
405 	  Support for error detection and correction on the
414 	  Support for error detection and correction on the
419 	bool "Altera On-Chip RAM ECC"
422 	  Support for error detection and correction on the
423 	  Altera On-Chip RAM Memory for Altera SoCs.
429 	  Support for error detection and correction on the
436 	  Support for error detection and correction on the
443 	  Support for error detection and correction on the
450 	  Support for error detection and correction on the
457 	  Support for error detection and correction on the
464 	  Support for error detection and correction on the
471 	  Support for error detection and correction on the SiFive SoCs.
477 	  Support for error correction and detection on the Marvell Aramada XP
484 	  Support for error detection and correction on the Synopsys DDR
488 	tristate "APM X-Gene SoC"
491 	  Support for error detection and correction on the
492 	  APM X-Gene family of SOCs.
498 	  Support for error detection and correction on the TI SoCs.
504 	  Support for error detection and correction on the
508 	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
518 	  Support for error detection and correction on the Aspeed AST BMC SoC.
521 	  will expose error counters via the EDAC kernel framework.
527 	  Support for error detection and correction on the
531 	tristate "ARM DMC-520 ECC"
534 	  Support for error detection and correction on the
535 	  SoCs with ARM DMC-520 DRAM controller.
541 	  This driver supports error detection and correction for the
549 	  Support for error detection and correction on the Nuvoton NPCM DDR
552 	  The memory controller supports single bit error correction, double bit
553 	  error detection (in-line ECC in which a section 1/8th of the memory
560 	  Support for error detection and correction on the Xilinx Versal DDR