511 	struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;  in xilinx_dpdma_sw_desc_set_dma_addrs()  local
514 	hw_desc->src_addr = lower_32_bits(dma_addr[0]);  in xilinx_dpdma_sw_desc_set_dma_addrs()
516 		hw_desc->addr_ext |=  in xilinx_dpdma_sw_desc_set_dma_addrs()
521 		u32 *addr = &hw_desc->src_addr2;  in xilinx_dpdma_sw_desc_set_dma_addrs()
526 			u32 *addr_ext = &hw_desc->addr_ext_23;  in xilinx_dpdma_sw_desc_set_dma_addrs()
600 		struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;  in xilinx_dpdma_chan_dump_tx_desc()  local
604 		dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);  in xilinx_dpdma_chan_dump_tx_desc()
605 		dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);  in xilinx_dpdma_chan_dump_tx_desc()
606 		dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);  in xilinx_dpdma_chan_dump_tx_desc()
607 		dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);  in xilinx_dpdma_chan_dump_tx_desc()
608 		dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);  in xilinx_dpdma_chan_dump_tx_desc()
609 		dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);  in xilinx_dpdma_chan_dump_tx_desc()
610 		dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);  in xilinx_dpdma_chan_dump_tx_desc()
611 		dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);  in xilinx_dpdma_chan_dump_tx_desc()
612 		dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);  in xilinx_dpdma_chan_dump_tx_desc()
613 		dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);  in xilinx_dpdma_chan_dump_tx_desc()
614 		dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);  in xilinx_dpdma_chan_dump_tx_desc()
615 		dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);  in xilinx_dpdma_chan_dump_tx_desc()
616 		dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);  in xilinx_dpdma_chan_dump_tx_desc()
617 		dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);  in xilinx_dpdma_chan_dump_tx_desc()
618 		dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);  in xilinx_dpdma_chan_dump_tx_desc()
619 		dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);  in xilinx_dpdma_chan_dump_tx_desc()
701 		struct xilinx_dpdma_hw_desc *hw_desc;  in xilinx_dpdma_chan_prep_cyclic()  local
716 		hw_desc = &sw_desc->hw;  in xilinx_dpdma_chan_prep_cyclic()
717 		hw_desc->xfer_size = period_len;  in xilinx_dpdma_chan_prep_cyclic()
718 		hw_desc->hsize_stride =  in xilinx_dpdma_chan_prep_cyclic()
723 		hw_desc->control = XILINX_DPDMA_DESC_CONTROL_PREEMBLE |  in xilinx_dpdma_chan_prep_cyclic()
768 	struct xilinx_dpdma_hw_desc *hw_desc;  in xilinx_dpdma_chan_prep_interleaved_dma()  local
792 	hw_desc = &sw_desc->hw;  in xilinx_dpdma_chan_prep_interleaved_dma()
794 	hw_desc->xfer_size = hsize * xt->numf;  in xilinx_dpdma_chan_prep_interleaved_dma()
795 	hw_desc->hsize_stride =  in xilinx_dpdma_chan_prep_interleaved_dma()
799 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;  in xilinx_dpdma_chan_prep_interleaved_dma()
800 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;  in xilinx_dpdma_chan_prep_interleaved_dma()
801 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;  in xilinx_dpdma_chan_prep_interleaved_dma()
802 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;  in xilinx_dpdma_chan_prep_interleaved_dma()