556 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,  in dma_ctrl_write()  function
565 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);  in dma_ctrl_clr()
571 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);  in dma_ctrl_set()
606 		dma_ctrl_write(chan, reg, addr);  in xilinx_write()
1405 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_vdma_start_transfer()
1490 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);  in xilinx_cdma_start_transfer()
1523 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_cdma_start_transfer()
1564 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1572 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1600 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_dma_start_transfer()
1649 	dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);  in xilinx_mcdma_start_transfer()
1658 	dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);  in xilinx_mcdma_start_transfer()
1663 	dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);  in xilinx_mcdma_start_transfer()
1832 	dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),  in xilinx_mcdma_irq_handler()
1883 	dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1896 		dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
2361 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_prep_dma_cyclic()
2510 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_terminate_all()
2593 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);  in xilinx_vdma_channel_set_config()