Lines Matching +full:tpl +full:- +full:support
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
11 #include <linux/dma-mapping.h>
26 #include <linux/soc/ti/k3-ringacc.h>
29 #include <linux/dma/k3-event-router.h>
30 #include <linux/dma/ti-cppi5.h>
32 #include "../virt-dma.h"
33 #include "k3-udma.h"
34 #include "k3-psil-priv.h"
359 if (!uc->tchan) in udma_tchanrt_read()
361 return udma_read(uc->tchan->reg_rt, reg); in udma_tchanrt_read()
366 if (!uc->tchan) in udma_tchanrt_write()
368 udma_write(uc->tchan->reg_rt, reg, val); in udma_tchanrt_write()
374 if (!uc->tchan) in udma_tchanrt_update_bits()
376 udma_update_bits(uc->tchan->reg_rt, reg, mask, val); in udma_tchanrt_update_bits()
382 if (!uc->rchan) in udma_rchanrt_read()
384 return udma_read(uc->rchan->reg_rt, reg); in udma_rchanrt_read()
389 if (!uc->rchan) in udma_rchanrt_write()
391 udma_write(uc->rchan->reg_rt, reg, val); in udma_rchanrt_write()
397 if (!uc->rchan) in udma_rchanrt_update_bits()
399 udma_update_bits(uc->rchan->reg_rt, reg, mask, val); in udma_rchanrt_update_bits()
404 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in navss_psil_pair()
407 return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci, in navss_psil_pair()
408 tisci_rm->tisci_navss_dev_id, in navss_psil_pair()
415 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in navss_psil_unpair()
418 return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci, in navss_psil_unpair()
419 tisci_rm->tisci_navss_dev_id, in navss_psil_unpair()
425 struct device *chan_dev = &chan->dev->device; in k3_configure_chan_coherency()
429 chan->dev->chan_dma_dev = false; in k3_configure_chan_coherency()
431 chan_dev->dma_coherent = false; in k3_configure_chan_coherency()
432 chan_dev->dma_parms = NULL; in k3_configure_chan_coherency()
434 chan->dev->chan_dma_dev = true; in k3_configure_chan_coherency()
436 chan_dev->dma_coherent = true; in k3_configure_chan_coherency()
438 chan_dev->dma_parms = chan_dev->parent->dma_parms; in k3_configure_chan_coherency()
440 dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel); in k3_configure_chan_coherency()
442 chan_dev->dma_coherent = false; in k3_configure_chan_coherency()
443 chan_dev->dma_parms = NULL; in k3_configure_chan_coherency()
451 for (i = 0; i < tpl_map->levels; i++) { in udma_get_chan_tpl_index()
452 if (chan_id >= tpl_map->start_idx[i]) in udma_get_chan_tpl_index()
461 memset(&uc->config, 0, sizeof(uc->config)); in udma_reset_uchan()
462 uc->config.remote_thread_id = -1; in udma_reset_uchan()
463 uc->config.mapped_channel_id = -1; in udma_reset_uchan()
464 uc->config.default_flow_id = -1; in udma_reset_uchan()
465 uc->state = UDMA_CHAN_IS_IDLE; in udma_reset_uchan()
470 struct device *dev = uc->ud->dev; in udma_dump_chan_stdata()
474 if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) { in udma_dump_chan_stdata()
483 if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) { in udma_dump_chan_stdata()
496 return d->hwdesc[idx].cppi5_desc_paddr; in udma_curr_cppi5_desc_paddr()
501 return d->hwdesc[idx].cppi5_desc_vaddr; in udma_curr_cppi5_desc_vaddr()
507 struct udma_desc *d = uc->terminated_desc; in udma_udma_desc_from_paddr()
511 d->desc_idx); in udma_udma_desc_from_paddr()
518 d = uc->desc; in udma_udma_desc_from_paddr()
521 d->desc_idx); in udma_udma_desc_from_paddr()
533 if (uc->use_dma_pool) { in udma_free_hwdesc()
536 for (i = 0; i < d->hwdesc_count; i++) { in udma_free_hwdesc()
537 if (!d->hwdesc[i].cppi5_desc_vaddr) in udma_free_hwdesc()
540 dma_pool_free(uc->hdesc_pool, in udma_free_hwdesc()
541 d->hwdesc[i].cppi5_desc_vaddr, in udma_free_hwdesc()
542 d->hwdesc[i].cppi5_desc_paddr); in udma_free_hwdesc()
544 d->hwdesc[i].cppi5_desc_vaddr = NULL; in udma_free_hwdesc()
546 } else if (d->hwdesc[0].cppi5_desc_vaddr) { in udma_free_hwdesc()
547 dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size, in udma_free_hwdesc()
548 d->hwdesc[0].cppi5_desc_vaddr, in udma_free_hwdesc()
549 d->hwdesc[0].cppi5_desc_paddr); in udma_free_hwdesc()
551 d->hwdesc[0].cppi5_desc_vaddr = NULL; in udma_free_hwdesc()
562 spin_lock_irqsave(&ud->lock, flags); in udma_purge_desc_work()
563 list_splice_tail_init(&ud->desc_to_purge, &head); in udma_purge_desc_work()
564 spin_unlock_irqrestore(&ud->lock, flags); in udma_purge_desc_work()
567 struct udma_chan *uc = to_udma_chan(vd->tx.chan); in udma_purge_desc_work()
568 struct udma_desc *d = to_udma_desc(&vd->tx); in udma_purge_desc_work()
571 list_del(&vd->node); in udma_purge_desc_work()
576 if (!list_empty(&ud->desc_to_purge)) in udma_purge_desc_work()
577 schedule_work(&ud->purge_work); in udma_purge_desc_work()
582 struct udma_dev *ud = to_udma_dev(vd->tx.chan->device); in udma_desc_free()
583 struct udma_chan *uc = to_udma_chan(vd->tx.chan); in udma_desc_free()
584 struct udma_desc *d = to_udma_desc(&vd->tx); in udma_desc_free()
587 if (uc->terminated_desc == d) in udma_desc_free()
588 uc->terminated_desc = NULL; in udma_desc_free()
590 if (uc->use_dma_pool) { in udma_desc_free()
596 spin_lock_irqsave(&ud->lock, flags); in udma_desc_free()
597 list_add_tail(&vd->node, &ud->desc_to_purge); in udma_desc_free()
598 spin_unlock_irqrestore(&ud->lock, flags); in udma_desc_free()
600 schedule_work(&ud->purge_work); in udma_desc_free()
608 if (uc->tchan) in udma_is_chan_running()
610 if (uc->rchan) in udma_is_chan_running()
623 switch (uc->config.dir) { in udma_is_chan_paused()
648 return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; in udma_get_rx_flush_hwdesc_paddr()
653 struct udma_desc *d = uc->desc; in udma_push_to_ring()
657 switch (uc->config.dir) { in udma_push_to_ring()
659 ring = uc->rflow->fd_ring; in udma_push_to_ring()
663 ring = uc->tchan->t_ring; in udma_push_to_ring()
666 return -EINVAL; in udma_push_to_ring()
669 /* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */ in udma_push_to_ring()
670 if (idx == -1) { in udma_push_to_ring()
683 if (uc->config.dir != DMA_DEV_TO_MEM) in udma_desc_is_rx_flush()
697 switch (uc->config.dir) { in udma_pop_from_ring()
699 ring = uc->rflow->r_ring; in udma_pop_from_ring()
703 ring = uc->tchan->tc_ring; in udma_pop_from_ring()
706 return -ENOENT; in udma_pop_from_ring()
721 return -ENOENT; in udma_pop_from_ring()
731 switch (uc->config.dir) { in udma_reset_rings()
733 if (uc->rchan) { in udma_reset_rings()
734 ring1 = uc->rflow->fd_ring; in udma_reset_rings()
735 ring2 = uc->rflow->r_ring; in udma_reset_rings()
740 if (uc->tchan) { in udma_reset_rings()
741 ring1 = uc->tchan->t_ring; in udma_reset_rings()
742 ring2 = uc->tchan->tc_ring; in udma_reset_rings()
756 if (uc->terminated_desc) { in udma_reset_rings()
757 udma_desc_free(&uc->terminated_desc->vd); in udma_reset_rings()
758 uc->terminated_desc = NULL; in udma_reset_rings()
764 if (uc->desc->dir == DMA_DEV_TO_MEM) { in udma_decrement_byte_counters()
767 if (uc->config.ep_type != PSIL_EP_NATIVE) in udma_decrement_byte_counters()
772 if (!uc->bchan && uc->config.ep_type != PSIL_EP_NATIVE) in udma_decrement_byte_counters()
781 if (uc->tchan) { in udma_reset_counters()
791 if (!uc->bchan) { in udma_reset_counters()
797 if (uc->rchan) { in udma_reset_counters()
814 switch (uc->config.dir) { in udma_reset_chan()
828 return -EINVAL; in udma_reset_chan()
834 /* Hard reset: re-initialize the channel to reset */ in udma_reset_chan()
839 memcpy(&ucc_backup, &uc->config, sizeof(uc->config)); in udma_reset_chan()
840 uc->ud->ddev.device_free_chan_resources(&uc->vc.chan); in udma_reset_chan()
843 memcpy(&uc->config, &ucc_backup, sizeof(uc->config)); in udma_reset_chan()
844 ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan); in udma_reset_chan()
852 if (uc->config.dir == DMA_DEV_TO_MEM) in udma_reset_chan()
858 uc->state = UDMA_CHAN_IS_IDLE; in udma_reset_chan()
865 struct udma_chan_config *ucc = &uc->config; in udma_start_desc()
867 if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode && in udma_start_desc()
868 (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) { in udma_start_desc()
874 * PKTDMA supports pre-linked descriptor and cyclic is not in udma_start_desc()
877 for (i = 0; i < uc->desc->sglen; i++) in udma_start_desc()
887 if (uc->config.ep_type == PSIL_EP_NATIVE) in udma_chan_needs_reconfiguration()
891 if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) in udma_chan_needs_reconfiguration()
899 struct virt_dma_desc *vd = vchan_next_desc(&uc->vc); in udma_start()
902 uc->desc = NULL; in udma_start()
903 return -ENOENT; in udma_start()
906 list_del(&vd->node); in udma_start()
908 uc->desc = to_udma_desc(&vd->tx); in udma_start()
922 switch (uc->desc->dir) { in udma_start()
925 if (uc->config.ep_type == PSIL_EP_PDMA_XY) { in udma_start()
926 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | in udma_start()
927 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); in udma_start()
929 uc->ud->match_data; in udma_start()
931 if (uc->config.enable_acc32) in udma_start()
933 if (uc->config.enable_burst) in udma_start()
942 PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt, in udma_start()
943 match_data->statictr_z_mask)); in udma_start()
946 memcpy(&uc->static_tr, &uc->desc->static_tr, in udma_start()
947 sizeof(uc->static_tr)); in udma_start()
960 if (uc->config.ep_type == PSIL_EP_PDMA_XY) { in udma_start()
961 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | in udma_start()
962 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); in udma_start()
964 if (uc->config.enable_acc32) in udma_start()
966 if (uc->config.enable_burst) in udma_start()
974 memcpy(&uc->static_tr, &uc->desc->static_tr, in udma_start()
975 sizeof(uc->static_tr)); in udma_start()
994 return -EINVAL; in udma_start()
997 uc->state = UDMA_CHAN_IS_ACTIVE; in udma_start()
1005 enum udma_chan_state old_state = uc->state; in udma_stop()
1007 uc->state = UDMA_CHAN_IS_TERMINATING; in udma_stop()
1008 reinit_completion(&uc->teardown_completed); in udma_stop()
1010 switch (uc->config.dir) { in udma_stop()
1012 if (!uc->cyclic && !uc->desc) in udma_stop()
1013 udma_push_to_ring(uc, -1); in udma_stop()
1033 uc->state = old_state; in udma_stop()
1034 complete_all(&uc->teardown_completed); in udma_stop()
1035 return -EINVAL; in udma_stop()
1043 struct udma_desc *d = uc->desc; in udma_cyclic_packet_elapsed()
1046 h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr; in udma_cyclic_packet_elapsed()
1048 udma_push_to_ring(uc, d->desc_idx); in udma_cyclic_packet_elapsed()
1049 d->desc_idx = (d->desc_idx + 1) % d->sglen; in udma_cyclic_packet_elapsed()
1054 struct cppi5_host_desc_t *h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_fetch_epib()
1056 memcpy(d->metadata, h_desc->epib, d->metadata_size); in udma_fetch_epib()
1069 if (uc->config.ep_type == PSIL_EP_NATIVE || in udma_is_desc_really_done()
1070 uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT)) in udma_is_desc_really_done()
1078 uc->tx_drain.residue = bcnt - peer_bcnt; in udma_is_desc_really_done()
1079 uc->tx_drain.tstamp = ktime_get(); in udma_is_desc_really_done()
1096 if (uc->desc) { in udma_check_tx_completion()
1098 residue_diff = uc->tx_drain.residue; in udma_check_tx_completion()
1099 time_diff = uc->tx_drain.tstamp; in udma_check_tx_completion()
1104 desc_done = udma_is_desc_really_done(uc, uc->desc); in udma_check_tx_completion()
1112 time_diff = ktime_sub(uc->tx_drain.tstamp, in udma_check_tx_completion()
1114 residue_diff -= uc->tx_drain.residue; in udma_check_tx_completion()
1123 uc->tx_drain.residue; in udma_check_tx_completion()
1126 schedule_delayed_work(&uc->tx_drain.work, HZ); in udma_check_tx_completion()
1135 if (uc->desc) { in udma_check_tx_completion()
1136 struct udma_desc *d = uc->desc; in udma_check_tx_completion()
1138 udma_decrement_byte_counters(uc, d->residue); in udma_check_tx_completion()
1140 vchan_cookie_complete(&d->vd); in udma_check_tx_completion()
1157 spin_lock(&uc->vc.lock); in udma_ring_irq_handler()
1161 complete_all(&uc->teardown_completed); in udma_ring_irq_handler()
1163 if (uc->terminated_desc) { in udma_ring_irq_handler()
1164 udma_desc_free(&uc->terminated_desc->vd); in udma_ring_irq_handler()
1165 uc->terminated_desc = NULL; in udma_ring_irq_handler()
1168 if (!uc->desc) in udma_ring_irq_handler()
1178 d->desc_idx); in udma_ring_irq_handler()
1180 dev_err(uc->ud->dev, "not matching descriptors!\n"); in udma_ring_irq_handler()
1184 if (d == uc->desc) { in udma_ring_irq_handler()
1186 if (uc->cyclic) { in udma_ring_irq_handler()
1188 vchan_cyclic_callback(&d->vd); in udma_ring_irq_handler()
1191 udma_decrement_byte_counters(uc, d->residue); in udma_ring_irq_handler()
1193 vchan_cookie_complete(&d->vd); in udma_ring_irq_handler()
1195 schedule_delayed_work(&uc->tx_drain.work, in udma_ring_irq_handler()
1204 dma_cookie_complete(&d->vd.tx); in udma_ring_irq_handler()
1208 spin_unlock(&uc->vc.lock); in udma_ring_irq_handler()
1218 spin_lock(&uc->vc.lock); in udma_udma_irq_handler()
1219 d = uc->desc; in udma_udma_irq_handler()
1221 d->tr_idx = (d->tr_idx + 1) % d->sglen; in udma_udma_irq_handler()
1223 if (uc->cyclic) { in udma_udma_irq_handler()
1224 vchan_cyclic_callback(&d->vd); in udma_udma_irq_handler()
1227 udma_decrement_byte_counters(uc, d->residue); in udma_udma_irq_handler()
1229 vchan_cookie_complete(&d->vd); in udma_udma_irq_handler()
1233 spin_unlock(&uc->vc.lock); in udma_udma_irq_handler()
1239 * __udma_alloc_gp_rflow_range - alloc range of GP RX flows
1245 * only using explicit flow id number. if @from is set to -1 it will try to find
1249 * Returns -ENOMEM if can't find free range.
1250 * -EEXIST if requested range is busy.
1251 * -EINVAL if wrong input values passed.
1261 tmp_from = ud->rchan_cnt; in __udma_alloc_gp_rflow_range()
1263 if (tmp_from < ud->rchan_cnt) in __udma_alloc_gp_rflow_range()
1264 return -EINVAL; in __udma_alloc_gp_rflow_range()
1266 if (tmp_from + cnt > ud->rflow_cnt) in __udma_alloc_gp_rflow_range()
1267 return -EINVAL; in __udma_alloc_gp_rflow_range()
1269 bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, in __udma_alloc_gp_rflow_range()
1270 ud->rflow_cnt); in __udma_alloc_gp_rflow_range()
1273 ud->rflow_cnt, in __udma_alloc_gp_rflow_range()
1275 if (start >= ud->rflow_cnt) in __udma_alloc_gp_rflow_range()
1276 return -ENOMEM; in __udma_alloc_gp_rflow_range()
1279 return -EEXIST; in __udma_alloc_gp_rflow_range()
1281 bitmap_set(ud->rflow_gp_map_allocated, start, cnt); in __udma_alloc_gp_rflow_range()
1287 if (from < ud->rchan_cnt) in __udma_free_gp_rflow_range()
1288 return -EINVAL; in __udma_free_gp_rflow_range()
1289 if (from + cnt > ud->rflow_cnt) in __udma_free_gp_rflow_range()
1290 return -EINVAL; in __udma_free_gp_rflow_range()
1292 bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); in __udma_free_gp_rflow_range()
1301 * TI-SCI FW will perform additional permission check ant way, it's in __udma_get_rflow()
1305 if (id < 0 || id >= ud->rflow_cnt) in __udma_get_rflow()
1306 return ERR_PTR(-ENOENT); in __udma_get_rflow()
1308 if (test_bit(id, ud->rflow_in_use)) in __udma_get_rflow()
1309 return ERR_PTR(-ENOENT); in __udma_get_rflow()
1311 if (ud->rflow_gp_map) { in __udma_get_rflow()
1313 if (!test_bit(id, ud->rflow_gp_map) && in __udma_get_rflow()
1314 !test_bit(id, ud->rflow_gp_map_allocated)) in __udma_get_rflow()
1315 return ERR_PTR(-EINVAL); in __udma_get_rflow()
1318 dev_dbg(ud->dev, "get rflow%d\n", id); in __udma_get_rflow()
1319 set_bit(id, ud->rflow_in_use); in __udma_get_rflow()
1320 return &ud->rflows[id]; in __udma_get_rflow()
1325 if (!test_bit(rflow->id, ud->rflow_in_use)) { in __udma_put_rflow()
1326 dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id); in __udma_put_rflow()
1330 dev_dbg(ud->dev, "put rflow%d\n", rflow->id); in __udma_put_rflow()
1331 clear_bit(rflow->id, ud->rflow_in_use); in __udma_put_rflow()
1336 enum udma_tp_level tpl, \
1340 if (test_bit(id, ud->res##_map)) { \
1341 dev_err(ud->dev, "res##%d is in use\n", id); \
1342 return ERR_PTR(-ENOENT); \
1347 if (tpl >= ud->res##_tpl.levels) \
1348 tpl = ud->res##_tpl.levels - 1; \
1350 start = ud->res##_tpl.start_idx[tpl]; \
1352 id = find_next_zero_bit(ud->res##_map, ud->res##_cnt, \
1354 if (id == ud->res##_cnt) { \
1355 return ERR_PTR(-ENOENT); \
1359 set_bit(id, ud->res##_map); \
1360 return &ud->res##s[id]; \
1369 struct udma_dev *ud = uc->ud; in bcdma_get_bchan()
1370 enum udma_tp_level tpl; in bcdma_get_bchan() local
1373 if (uc->bchan) { in bcdma_get_bchan()
1374 dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n", in bcdma_get_bchan()
1375 uc->id, uc->bchan->id); in bcdma_get_bchan()
1380 * Use normal channels for peripherals, and highest TPL channel for in bcdma_get_bchan()
1383 if (uc->config.tr_trigger_type) in bcdma_get_bchan()
1384 tpl = 0; in bcdma_get_bchan()
1386 tpl = ud->bchan_tpl.levels - 1; in bcdma_get_bchan()
1388 uc->bchan = __udma_reserve_bchan(ud, tpl, -1); in bcdma_get_bchan()
1389 if (IS_ERR(uc->bchan)) { in bcdma_get_bchan()
1390 ret = PTR_ERR(uc->bchan); in bcdma_get_bchan()
1391 uc->bchan = NULL; in bcdma_get_bchan()
1395 uc->tchan = uc->bchan; in bcdma_get_bchan()
1402 struct udma_dev *ud = uc->ud; in udma_get_tchan()
1405 if (uc->tchan) { in udma_get_tchan()
1406 dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n", in udma_get_tchan()
1407 uc->id, uc->tchan->id); in udma_get_tchan()
1412 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. in udma_get_tchan()
1416 uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, in udma_get_tchan()
1417 uc->config.mapped_channel_id); in udma_get_tchan()
1418 if (IS_ERR(uc->tchan)) { in udma_get_tchan()
1419 ret = PTR_ERR(uc->tchan); in udma_get_tchan()
1420 uc->tchan = NULL; in udma_get_tchan()
1424 if (ud->tflow_cnt) { in udma_get_tchan()
1427 /* Only PKTDMA have support for tx flows */ in udma_get_tchan()
1428 if (uc->config.default_flow_id >= 0) in udma_get_tchan()
1429 tflow_id = uc->config.default_flow_id; in udma_get_tchan()
1431 tflow_id = uc->tchan->id; in udma_get_tchan()
1433 if (test_bit(tflow_id, ud->tflow_map)) { in udma_get_tchan()
1434 dev_err(ud->dev, "tflow%d is in use\n", tflow_id); in udma_get_tchan()
1435 clear_bit(uc->tchan->id, ud->tchan_map); in udma_get_tchan()
1436 uc->tchan = NULL; in udma_get_tchan()
1437 return -ENOENT; in udma_get_tchan()
1440 uc->tchan->tflow_id = tflow_id; in udma_get_tchan()
1441 set_bit(tflow_id, ud->tflow_map); in udma_get_tchan()
1443 uc->tchan->tflow_id = -1; in udma_get_tchan()
1451 struct udma_dev *ud = uc->ud; in udma_get_rchan()
1454 if (uc->rchan) { in udma_get_rchan()
1455 dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n", in udma_get_rchan()
1456 uc->id, uc->rchan->id); in udma_get_rchan()
1461 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. in udma_get_rchan()
1465 uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, in udma_get_rchan()
1466 uc->config.mapped_channel_id); in udma_get_rchan()
1467 if (IS_ERR(uc->rchan)) { in udma_get_rchan()
1468 ret = PTR_ERR(uc->rchan); in udma_get_rchan()
1469 uc->rchan = NULL; in udma_get_rchan()
1478 struct udma_dev *ud = uc->ud; in udma_get_chan_pair()
1481 if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) { in udma_get_chan_pair()
1482 dev_info(ud->dev, "chan%d: already have %d pair allocated\n", in udma_get_chan_pair()
1483 uc->id, uc->tchan->id); in udma_get_chan_pair()
1487 if (uc->tchan) { in udma_get_chan_pair()
1488 dev_err(ud->dev, "chan%d: already have tchan%d allocated\n", in udma_get_chan_pair()
1489 uc->id, uc->tchan->id); in udma_get_chan_pair()
1490 return -EBUSY; in udma_get_chan_pair()
1491 } else if (uc->rchan) { in udma_get_chan_pair()
1492 dev_err(ud->dev, "chan%d: already have rchan%d allocated\n", in udma_get_chan_pair()
1493 uc->id, uc->rchan->id); in udma_get_chan_pair()
1494 return -EBUSY; in udma_get_chan_pair()
1498 end = min(ud->tchan_cnt, ud->rchan_cnt); in udma_get_chan_pair()
1500 * Try to use the highest TPL channel pair for MEM_TO_MEM channels in udma_get_chan_pair()
1501 * Note: in UDMAP the channel TPL is symmetric between tchan and rchan in udma_get_chan_pair()
1503 chan_id = ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1]; in udma_get_chan_pair()
1505 if (!test_bit(chan_id, ud->tchan_map) && in udma_get_chan_pair()
1506 !test_bit(chan_id, ud->rchan_map)) in udma_get_chan_pair()
1511 return -ENOENT; in udma_get_chan_pair()
1513 set_bit(chan_id, ud->tchan_map); in udma_get_chan_pair()
1514 set_bit(chan_id, ud->rchan_map); in udma_get_chan_pair()
1515 uc->tchan = &ud->tchans[chan_id]; in udma_get_chan_pair()
1516 uc->rchan = &ud->rchans[chan_id]; in udma_get_chan_pair()
1519 uc->tchan->tflow_id = -1; in udma_get_chan_pair()
1526 struct udma_dev *ud = uc->ud; in udma_get_rflow()
1529 if (!uc->rchan) { in udma_get_rflow()
1530 dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id); in udma_get_rflow()
1531 return -EINVAL; in udma_get_rflow()
1534 if (uc->rflow) { in udma_get_rflow()
1535 dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n", in udma_get_rflow()
1536 uc->id, uc->rflow->id); in udma_get_rflow()
1540 uc->rflow = __udma_get_rflow(ud, flow_id); in udma_get_rflow()
1541 if (IS_ERR(uc->rflow)) { in udma_get_rflow()
1542 ret = PTR_ERR(uc->rflow); in udma_get_rflow()
1543 uc->rflow = NULL; in udma_get_rflow()
1552 struct udma_dev *ud = uc->ud; in bcdma_put_bchan()
1554 if (uc->bchan) { in bcdma_put_bchan()
1555 dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id, in bcdma_put_bchan()
1556 uc->bchan->id); in bcdma_put_bchan()
1557 clear_bit(uc->bchan->id, ud->bchan_map); in bcdma_put_bchan()
1558 uc->bchan = NULL; in bcdma_put_bchan()
1559 uc->tchan = NULL; in bcdma_put_bchan()
1565 struct udma_dev *ud = uc->ud; in udma_put_rchan()
1567 if (uc->rchan) { in udma_put_rchan()
1568 dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id, in udma_put_rchan()
1569 uc->rchan->id); in udma_put_rchan()
1570 clear_bit(uc->rchan->id, ud->rchan_map); in udma_put_rchan()
1571 uc->rchan = NULL; in udma_put_rchan()
1577 struct udma_dev *ud = uc->ud; in udma_put_tchan()
1579 if (uc->tchan) { in udma_put_tchan()
1580 dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id, in udma_put_tchan()
1581 uc->tchan->id); in udma_put_tchan()
1582 clear_bit(uc->tchan->id, ud->tchan_map); in udma_put_tchan()
1584 if (uc->tchan->tflow_id >= 0) in udma_put_tchan()
1585 clear_bit(uc->tchan->tflow_id, ud->tflow_map); in udma_put_tchan()
1587 uc->tchan = NULL; in udma_put_tchan()
1593 struct udma_dev *ud = uc->ud; in udma_put_rflow()
1595 if (uc->rflow) { in udma_put_rflow()
1596 dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id, in udma_put_rflow()
1597 uc->rflow->id); in udma_put_rflow()
1598 __udma_put_rflow(ud, uc->rflow); in udma_put_rflow()
1599 uc->rflow = NULL; in udma_put_rflow()
1605 if (!uc->bchan) in bcdma_free_bchan_resources()
1608 k3_ringacc_ring_free(uc->bchan->tc_ring); in bcdma_free_bchan_resources()
1609 k3_ringacc_ring_free(uc->bchan->t_ring); in bcdma_free_bchan_resources()
1610 uc->bchan->tc_ring = NULL; in bcdma_free_bchan_resources()
1611 uc->bchan->t_ring = NULL; in bcdma_free_bchan_resources()
1612 k3_configure_chan_coherency(&uc->vc.chan, 0); in bcdma_free_bchan_resources()
1620 struct udma_dev *ud = uc->ud; in bcdma_alloc_bchan_resources()
1627 ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1, in bcdma_alloc_bchan_resources()
1628 &uc->bchan->t_ring, in bcdma_alloc_bchan_resources()
1629 &uc->bchan->tc_ring); in bcdma_alloc_bchan_resources()
1631 ret = -EBUSY; in bcdma_alloc_bchan_resources()
1640 k3_configure_chan_coherency(&uc->vc.chan, ud->asel); in bcdma_alloc_bchan_resources()
1641 ring_cfg.asel = ud->asel; in bcdma_alloc_bchan_resources()
1642 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); in bcdma_alloc_bchan_resources()
1644 ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg); in bcdma_alloc_bchan_resources()
1651 k3_ringacc_ring_free(uc->bchan->tc_ring); in bcdma_alloc_bchan_resources()
1652 uc->bchan->tc_ring = NULL; in bcdma_alloc_bchan_resources()
1653 k3_ringacc_ring_free(uc->bchan->t_ring); in bcdma_alloc_bchan_resources()
1654 uc->bchan->t_ring = NULL; in bcdma_alloc_bchan_resources()
1655 k3_configure_chan_coherency(&uc->vc.chan, 0); in bcdma_alloc_bchan_resources()
1664 if (!uc->tchan) in udma_free_tx_resources()
1667 k3_ringacc_ring_free(uc->tchan->t_ring); in udma_free_tx_resources()
1668 k3_ringacc_ring_free(uc->tchan->tc_ring); in udma_free_tx_resources()
1669 uc->tchan->t_ring = NULL; in udma_free_tx_resources()
1670 uc->tchan->tc_ring = NULL; in udma_free_tx_resources()
1678 struct udma_dev *ud = uc->ud; in udma_alloc_tx_resources()
1686 tchan = uc->tchan; in udma_alloc_tx_resources()
1687 if (tchan->tflow_id >= 0) in udma_alloc_tx_resources()
1688 ring_idx = tchan->tflow_id; in udma_alloc_tx_resources()
1690 ring_idx = ud->bchan_cnt + tchan->id; in udma_alloc_tx_resources()
1692 ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, in udma_alloc_tx_resources()
1693 &tchan->t_ring, in udma_alloc_tx_resources()
1694 &tchan->tc_ring); in udma_alloc_tx_resources()
1696 ret = -EBUSY; in udma_alloc_tx_resources()
1703 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_alloc_tx_resources()
1708 k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); in udma_alloc_tx_resources()
1709 ring_cfg.asel = uc->config.asel; in udma_alloc_tx_resources()
1710 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); in udma_alloc_tx_resources()
1713 ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg); in udma_alloc_tx_resources()
1714 ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg); in udma_alloc_tx_resources()
1722 k3_ringacc_ring_free(uc->tchan->tc_ring); in udma_alloc_tx_resources()
1723 uc->tchan->tc_ring = NULL; in udma_alloc_tx_resources()
1724 k3_ringacc_ring_free(uc->tchan->t_ring); in udma_alloc_tx_resources()
1725 uc->tchan->t_ring = NULL; in udma_alloc_tx_resources()
1734 if (!uc->rchan) in udma_free_rx_resources()
1737 if (uc->rflow) { in udma_free_rx_resources()
1738 struct udma_rflow *rflow = uc->rflow; in udma_free_rx_resources()
1740 k3_ringacc_ring_free(rflow->fd_ring); in udma_free_rx_resources()
1741 k3_ringacc_ring_free(rflow->r_ring); in udma_free_rx_resources()
1742 rflow->fd_ring = NULL; in udma_free_rx_resources()
1743 rflow->r_ring = NULL; in udma_free_rx_resources()
1753 struct udma_dev *ud = uc->ud; in udma_alloc_rx_resources()
1764 if (uc->config.dir == DMA_MEM_TO_MEM) in udma_alloc_rx_resources()
1767 if (uc->config.default_flow_id >= 0) in udma_alloc_rx_resources()
1768 ret = udma_get_rflow(uc, uc->config.default_flow_id); in udma_alloc_rx_resources()
1770 ret = udma_get_rflow(uc, uc->rchan->id); in udma_alloc_rx_resources()
1773 ret = -EBUSY; in udma_alloc_rx_resources()
1777 rflow = uc->rflow; in udma_alloc_rx_resources()
1778 if (ud->tflow_cnt) in udma_alloc_rx_resources()
1779 fd_ring_id = ud->tflow_cnt + rflow->id; in udma_alloc_rx_resources()
1781 fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt + in udma_alloc_rx_resources()
1782 uc->rchan->id; in udma_alloc_rx_resources()
1784 ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1, in udma_alloc_rx_resources()
1785 &rflow->fd_ring, &rflow->r_ring); in udma_alloc_rx_resources()
1787 ret = -EBUSY; in udma_alloc_rx_resources()
1794 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_alloc_rx_resources()
1795 if (uc->config.pkt_mode) in udma_alloc_rx_resources()
1805 k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); in udma_alloc_rx_resources()
1806 ring_cfg.asel = uc->config.asel; in udma_alloc_rx_resources()
1807 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); in udma_alloc_rx_resources()
1810 ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg); in udma_alloc_rx_resources()
1813 ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg); in udma_alloc_rx_resources()
1821 k3_ringacc_ring_free(rflow->r_ring); in udma_alloc_rx_resources()
1822 rflow->r_ring = NULL; in udma_alloc_rx_resources()
1823 k3_ringacc_ring_free(rflow->fd_ring); in udma_alloc_rx_resources()
1824 rflow->fd_ring = NULL; in udma_alloc_rx_resources()
1867 struct udma_dev *ud = uc->ud; in udma_tisci_m2m_channel_config()
1868 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_tisci_m2m_channel_config()
1869 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in udma_tisci_m2m_channel_config()
1870 struct udma_tchan *tchan = uc->tchan; in udma_tisci_m2m_channel_config()
1871 struct udma_rchan *rchan = uc->rchan; in udma_tisci_m2m_channel_config()
1874 u8 tpl; in udma_tisci_m2m_channel_config() local
1876 /* Non synchronized - mem to mem type of transfer */ in udma_tisci_m2m_channel_config()
1877 int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring); in udma_tisci_m2m_channel_config()
1881 if (ud->match_data->flags & UDMA_FLAG_BURST_SIZE) { in udma_tisci_m2m_channel_config()
1882 tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, tchan->id); in udma_tisci_m2m_channel_config()
1884 burst_size = ud->match_data->burst_size[tpl]; in udma_tisci_m2m_channel_config()
1888 req_tx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_m2m_channel_config()
1889 req_tx.index = tchan->id; in udma_tisci_m2m_channel_config()
1893 req_tx.tx_atype = ud->atype; in udma_tisci_m2m_channel_config()
1899 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in udma_tisci_m2m_channel_config()
1901 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); in udma_tisci_m2m_channel_config()
1906 req_rx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_m2m_channel_config()
1907 req_rx.index = rchan->id; in udma_tisci_m2m_channel_config()
1911 req_rx.rx_atype = ud->atype; in udma_tisci_m2m_channel_config()
1917 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in udma_tisci_m2m_channel_config()
1919 dev_err(ud->dev, "rchan%d alloc failed %d\n", rchan->id, ret); in udma_tisci_m2m_channel_config()
1926 struct udma_dev *ud = uc->ud; in bcdma_tisci_m2m_channel_config()
1927 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_tisci_m2m_channel_config()
1928 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in bcdma_tisci_m2m_channel_config()
1930 struct udma_bchan *bchan = uc->bchan; in bcdma_tisci_m2m_channel_config()
1933 u8 tpl; in bcdma_tisci_m2m_channel_config() local
1935 if (ud->match_data->flags & UDMA_FLAG_BURST_SIZE) { in bcdma_tisci_m2m_channel_config()
1936 tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, bchan->id); in bcdma_tisci_m2m_channel_config()
1938 burst_size = ud->match_data->burst_size[tpl]; in bcdma_tisci_m2m_channel_config()
1942 req_tx.nav_id = tisci_rm->tisci_dev_id; in bcdma_tisci_m2m_channel_config()
1944 req_tx.index = bchan->id; in bcdma_tisci_m2m_channel_config()
1950 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in bcdma_tisci_m2m_channel_config()
1952 dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret); in bcdma_tisci_m2m_channel_config()
1959 struct udma_dev *ud = uc->ud; in udma_tisci_tx_channel_config()
1960 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_tisci_tx_channel_config()
1961 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in udma_tisci_tx_channel_config()
1962 struct udma_tchan *tchan = uc->tchan; in udma_tisci_tx_channel_config()
1963 int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring); in udma_tisci_tx_channel_config()
1968 if (uc->config.pkt_mode) { in udma_tisci_tx_channel_config()
1970 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, in udma_tisci_tx_channel_config()
1971 uc->config.psd_size, 0); in udma_tisci_tx_channel_config()
1978 req_tx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_tx_channel_config()
1979 req_tx.index = tchan->id; in udma_tisci_tx_channel_config()
1981 req_tx.tx_supr_tdpkt = uc->config.notdpkt; in udma_tisci_tx_channel_config()
1984 req_tx.tx_atype = uc->config.atype; in udma_tisci_tx_channel_config()
1985 if (uc->config.ep_type == PSIL_EP_PDMA_XY && in udma_tisci_tx_channel_config()
1986 ud->match_data->flags & UDMA_FLAG_TDTYPE) { in udma_tisci_tx_channel_config()
1993 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in udma_tisci_tx_channel_config()
1995 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); in udma_tisci_tx_channel_config()
2002 struct udma_dev *ud = uc->ud; in bcdma_tisci_tx_channel_config()
2003 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_tisci_tx_channel_config()
2004 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in bcdma_tisci_tx_channel_config()
2005 struct udma_tchan *tchan = uc->tchan; in bcdma_tisci_tx_channel_config()
2010 req_tx.nav_id = tisci_rm->tisci_dev_id; in bcdma_tisci_tx_channel_config()
2011 req_tx.index = tchan->id; in bcdma_tisci_tx_channel_config()
2012 req_tx.tx_supr_tdpkt = uc->config.notdpkt; in bcdma_tisci_tx_channel_config()
2013 if (ud->match_data->flags & UDMA_FLAG_TDTYPE) { in bcdma_tisci_tx_channel_config()
2020 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in bcdma_tisci_tx_channel_config()
2022 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); in bcdma_tisci_tx_channel_config()
2031 struct udma_dev *ud = uc->ud; in udma_tisci_rx_channel_config()
2032 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_tisci_rx_channel_config()
2033 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in udma_tisci_rx_channel_config()
2034 struct udma_rchan *rchan = uc->rchan; in udma_tisci_rx_channel_config()
2035 int fd_ring = k3_ringacc_get_ring_id(uc->rflow->fd_ring); in udma_tisci_rx_channel_config()
2036 int rx_ring = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_tisci_rx_channel_config()
2042 if (uc->config.pkt_mode) { in udma_tisci_rx_channel_config()
2044 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, in udma_tisci_rx_channel_config()
2045 uc->config.psd_size, 0); in udma_tisci_rx_channel_config()
2052 req_rx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_rx_channel_config()
2053 req_rx.index = rchan->id; in udma_tisci_rx_channel_config()
2057 req_rx.rx_atype = uc->config.atype; in udma_tisci_rx_channel_config()
2059 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in udma_tisci_rx_channel_config()
2061 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret); in udma_tisci_rx_channel_config()
2080 flow_req.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_rx_channel_config()
2081 flow_req.flow_index = rchan->id; in udma_tisci_rx_channel_config()
2083 if (uc->config.needs_epib) in udma_tisci_rx_channel_config()
2087 if (uc->config.psd_size) in udma_tisci_rx_channel_config()
2102 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); in udma_tisci_rx_channel_config()
2105 dev_err(ud->dev, "flow%d config failed: %d\n", rchan->id, ret); in udma_tisci_rx_channel_config()
2112 struct udma_dev *ud = uc->ud; in bcdma_tisci_rx_channel_config()
2113 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_tisci_rx_channel_config()
2114 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in bcdma_tisci_rx_channel_config()
2115 struct udma_rchan *rchan = uc->rchan; in bcdma_tisci_rx_channel_config()
2120 req_rx.nav_id = tisci_rm->tisci_dev_id; in bcdma_tisci_rx_channel_config()
2121 req_rx.index = rchan->id; in bcdma_tisci_rx_channel_config()
2123 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in bcdma_tisci_rx_channel_config()
2125 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret); in bcdma_tisci_rx_channel_config()
2132 struct udma_dev *ud = uc->ud; in pktdma_tisci_rx_channel_config()
2133 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in pktdma_tisci_rx_channel_config()
2134 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in pktdma_tisci_rx_channel_config()
2140 req_rx.nav_id = tisci_rm->tisci_dev_id; in pktdma_tisci_rx_channel_config()
2141 req_rx.index = uc->rchan->id; in pktdma_tisci_rx_channel_config()
2143 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in pktdma_tisci_rx_channel_config()
2145 dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret); in pktdma_tisci_rx_channel_config()
2154 flow_req.nav_id = tisci_rm->tisci_dev_id; in pktdma_tisci_rx_channel_config()
2155 flow_req.flow_index = uc->rflow->id; in pktdma_tisci_rx_channel_config()
2157 if (uc->config.needs_epib) in pktdma_tisci_rx_channel_config()
2161 if (uc->config.psd_size) in pktdma_tisci_rx_channel_config()
2167 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); in pktdma_tisci_rx_channel_config()
2170 dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id, in pktdma_tisci_rx_channel_config()
2179 struct udma_dev *ud = to_udma_dev(chan->device); in udma_alloc_chan_resources()
2180 const struct udma_soc_data *soc_data = ud->soc_data; in udma_alloc_chan_resources()
2185 uc->dma_dev = ud->dev; in udma_alloc_chan_resources()
2187 if (uc->config.pkt_mode || uc->config.dir == DMA_MEM_TO_MEM) { in udma_alloc_chan_resources()
2188 uc->use_dma_pool = true; in udma_alloc_chan_resources()
2190 if (uc->config.dir == DMA_MEM_TO_MEM) { in udma_alloc_chan_resources()
2191 uc->config.hdesc_size = cppi5_trdesc_calc_size( in udma_alloc_chan_resources()
2193 uc->config.pkt_mode = false; in udma_alloc_chan_resources()
2197 if (uc->use_dma_pool) { in udma_alloc_chan_resources()
2198 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev, in udma_alloc_chan_resources()
2199 uc->config.hdesc_size, in udma_alloc_chan_resources()
2200 ud->desc_align, in udma_alloc_chan_resources()
2202 if (!uc->hdesc_pool) { in udma_alloc_chan_resources()
2203 dev_err(ud->ddev.dev, in udma_alloc_chan_resources()
2205 uc->use_dma_pool = false; in udma_alloc_chan_resources()
2206 ret = -ENOMEM; in udma_alloc_chan_resources()
2215 reinit_completion(&uc->teardown_completed); in udma_alloc_chan_resources()
2216 complete_all(&uc->teardown_completed); in udma_alloc_chan_resources()
2217 uc->state = UDMA_CHAN_IS_IDLE; in udma_alloc_chan_resources()
2219 switch (uc->config.dir) { in udma_alloc_chan_resources()
2221 /* Non synchronized - mem to mem type of transfer */ in udma_alloc_chan_resources()
2222 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__, in udma_alloc_chan_resources()
2223 uc->id); in udma_alloc_chan_resources()
2241 uc->config.src_thread = ud->psil_base + uc->tchan->id; in udma_alloc_chan_resources()
2242 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in udma_alloc_chan_resources()
2245 irq_ring = uc->tchan->tc_ring; in udma_alloc_chan_resources()
2246 irq_udma_idx = uc->tchan->id; in udma_alloc_chan_resources()
2251 /* Slave transfer synchronized - mem to dev (TX) trasnfer */ in udma_alloc_chan_resources()
2252 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, in udma_alloc_chan_resources()
2253 uc->id); in udma_alloc_chan_resources()
2259 uc->config.src_thread = ud->psil_base + uc->tchan->id; in udma_alloc_chan_resources()
2260 uc->config.dst_thread = uc->config.remote_thread_id; in udma_alloc_chan_resources()
2261 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; in udma_alloc_chan_resources()
2263 irq_ring = uc->tchan->tc_ring; in udma_alloc_chan_resources()
2264 irq_udma_idx = uc->tchan->id; in udma_alloc_chan_resources()
2269 /* Slave transfer synchronized - dev to mem (RX) trasnfer */ in udma_alloc_chan_resources()
2270 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, in udma_alloc_chan_resources()
2271 uc->id); in udma_alloc_chan_resources()
2277 uc->config.src_thread = uc->config.remote_thread_id; in udma_alloc_chan_resources()
2278 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in udma_alloc_chan_resources()
2281 irq_ring = uc->rflow->r_ring; in udma_alloc_chan_resources()
2282 irq_udma_idx = soc_data->oes.udma_rchan + uc->rchan->id; in udma_alloc_chan_resources()
2288 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", in udma_alloc_chan_resources()
2289 __func__, uc->id, uc->config.dir); in udma_alloc_chan_resources()
2290 ret = -EINVAL; in udma_alloc_chan_resources()
2300 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); in udma_alloc_chan_resources()
2303 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); in udma_alloc_chan_resources()
2304 ret = -EBUSY; in udma_alloc_chan_resources()
2309 /* PSI-L pairing */ in udma_alloc_chan_resources()
2310 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); in udma_alloc_chan_resources()
2312 dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", in udma_alloc_chan_resources()
2313 uc->config.src_thread, uc->config.dst_thread); in udma_alloc_chan_resources()
2317 uc->psil_paired = true; in udma_alloc_chan_resources()
2319 uc->irq_num_ring = k3_ringacc_get_ring_irq_num(irq_ring); in udma_alloc_chan_resources()
2320 if (uc->irq_num_ring <= 0) { in udma_alloc_chan_resources()
2321 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n", in udma_alloc_chan_resources()
2323 ret = -EINVAL; in udma_alloc_chan_resources()
2327 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, in udma_alloc_chan_resources()
2328 IRQF_TRIGGER_HIGH, uc->name, uc); in udma_alloc_chan_resources()
2330 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); in udma_alloc_chan_resources()
2335 if (is_slave_direction(uc->config.dir) && !uc->config.pkt_mode) { in udma_alloc_chan_resources()
2336 uc->irq_num_udma = msi_get_virq(ud->dev, irq_udma_idx); in udma_alloc_chan_resources()
2337 if (uc->irq_num_udma <= 0) { in udma_alloc_chan_resources()
2338 dev_err(ud->dev, "Failed to get udma irq (index: %u)\n", in udma_alloc_chan_resources()
2340 free_irq(uc->irq_num_ring, uc); in udma_alloc_chan_resources()
2341 ret = -EINVAL; in udma_alloc_chan_resources()
2345 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0, in udma_alloc_chan_resources()
2346 uc->name, uc); in udma_alloc_chan_resources()
2348 dev_err(ud->dev, "chan%d: UDMA irq request failed\n", in udma_alloc_chan_resources()
2349 uc->id); in udma_alloc_chan_resources()
2350 free_irq(uc->irq_num_ring, uc); in udma_alloc_chan_resources()
2354 uc->irq_num_udma = 0; in udma_alloc_chan_resources()
2362 uc->irq_num_ring = 0; in udma_alloc_chan_resources()
2363 uc->irq_num_udma = 0; in udma_alloc_chan_resources()
2365 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); in udma_alloc_chan_resources()
2366 uc->psil_paired = false; in udma_alloc_chan_resources()
2373 if (uc->use_dma_pool) { in udma_alloc_chan_resources()
2374 dma_pool_destroy(uc->hdesc_pool); in udma_alloc_chan_resources()
2375 uc->use_dma_pool = false; in udma_alloc_chan_resources()
2384 struct udma_dev *ud = to_udma_dev(chan->device); in bcdma_alloc_chan_resources()
2385 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in bcdma_alloc_chan_resources()
2390 uc->config.pkt_mode = false; in bcdma_alloc_chan_resources()
2396 reinit_completion(&uc->teardown_completed); in bcdma_alloc_chan_resources()
2397 complete_all(&uc->teardown_completed); in bcdma_alloc_chan_resources()
2398 uc->state = UDMA_CHAN_IS_IDLE; in bcdma_alloc_chan_resources()
2400 switch (uc->config.dir) { in bcdma_alloc_chan_resources()
2402 /* Non synchronized - mem to mem type of transfer */ in bcdma_alloc_chan_resources()
2403 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__, in bcdma_alloc_chan_resources()
2404 uc->id); in bcdma_alloc_chan_resources()
2410 irq_ring_idx = uc->bchan->id + oes->bcdma_bchan_ring; in bcdma_alloc_chan_resources()
2411 irq_udma_idx = uc->bchan->id + oes->bcdma_bchan_data; in bcdma_alloc_chan_resources()
2416 /* Slave transfer synchronized - mem to dev (TX) trasnfer */ in bcdma_alloc_chan_resources()
2417 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, in bcdma_alloc_chan_resources()
2418 uc->id); in bcdma_alloc_chan_resources()
2422 uc->config.remote_thread_id = -1; in bcdma_alloc_chan_resources()
2426 uc->config.src_thread = ud->psil_base + uc->tchan->id; in bcdma_alloc_chan_resources()
2427 uc->config.dst_thread = uc->config.remote_thread_id; in bcdma_alloc_chan_resources()
2428 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; in bcdma_alloc_chan_resources()
2430 irq_ring_idx = uc->tchan->id + oes->bcdma_tchan_ring; in bcdma_alloc_chan_resources()
2431 irq_udma_idx = uc->tchan->id + oes->bcdma_tchan_data; in bcdma_alloc_chan_resources()
2436 /* Slave transfer synchronized - dev to mem (RX) trasnfer */ in bcdma_alloc_chan_resources()
2437 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, in bcdma_alloc_chan_resources()
2438 uc->id); in bcdma_alloc_chan_resources()
2442 uc->config.remote_thread_id = -1; in bcdma_alloc_chan_resources()
2446 uc->config.src_thread = uc->config.remote_thread_id; in bcdma_alloc_chan_resources()
2447 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in bcdma_alloc_chan_resources()
2450 irq_ring_idx = uc->rchan->id + oes->bcdma_rchan_ring; in bcdma_alloc_chan_resources()
2451 irq_udma_idx = uc->rchan->id + oes->bcdma_rchan_data; in bcdma_alloc_chan_resources()
2457 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", in bcdma_alloc_chan_resources()
2458 __func__, uc->id, uc->config.dir); in bcdma_alloc_chan_resources()
2459 return -EINVAL; in bcdma_alloc_chan_resources()
2467 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); in bcdma_alloc_chan_resources()
2470 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); in bcdma_alloc_chan_resources()
2471 ret = -EBUSY; in bcdma_alloc_chan_resources()
2476 uc->dma_dev = dmaengine_get_dma_device(chan); in bcdma_alloc_chan_resources()
2477 if (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type) { in bcdma_alloc_chan_resources()
2478 uc->config.hdesc_size = cppi5_trdesc_calc_size( in bcdma_alloc_chan_resources()
2481 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev, in bcdma_alloc_chan_resources()
2482 uc->config.hdesc_size, in bcdma_alloc_chan_resources()
2483 ud->desc_align, in bcdma_alloc_chan_resources()
2485 if (!uc->hdesc_pool) { in bcdma_alloc_chan_resources()
2486 dev_err(ud->ddev.dev, in bcdma_alloc_chan_resources()
2488 uc->use_dma_pool = false; in bcdma_alloc_chan_resources()
2489 ret = -ENOMEM; in bcdma_alloc_chan_resources()
2493 uc->use_dma_pool = true; in bcdma_alloc_chan_resources()
2494 } else if (uc->config.dir != DMA_MEM_TO_MEM) { in bcdma_alloc_chan_resources()
2495 /* PSI-L pairing */ in bcdma_alloc_chan_resources()
2496 ret = navss_psil_pair(ud, uc->config.src_thread, in bcdma_alloc_chan_resources()
2497 uc->config.dst_thread); in bcdma_alloc_chan_resources()
2499 dev_err(ud->dev, in bcdma_alloc_chan_resources()
2500 "PSI-L pairing failed: 0x%04x -> 0x%04x\n", in bcdma_alloc_chan_resources()
2501 uc->config.src_thread, uc->config.dst_thread); in bcdma_alloc_chan_resources()
2505 uc->psil_paired = true; in bcdma_alloc_chan_resources()
2508 uc->irq_num_ring = msi_get_virq(ud->dev, irq_ring_idx); in bcdma_alloc_chan_resources()
2509 if (uc->irq_num_ring <= 0) { in bcdma_alloc_chan_resources()
2510 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n", in bcdma_alloc_chan_resources()
2512 ret = -EINVAL; in bcdma_alloc_chan_resources()
2516 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, in bcdma_alloc_chan_resources()
2517 IRQF_TRIGGER_HIGH, uc->name, uc); in bcdma_alloc_chan_resources()
2519 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); in bcdma_alloc_chan_resources()
2524 if (is_slave_direction(uc->config.dir)) { in bcdma_alloc_chan_resources()
2525 uc->irq_num_udma = msi_get_virq(ud->dev, irq_udma_idx); in bcdma_alloc_chan_resources()
2526 if (uc->irq_num_udma <= 0) { in bcdma_alloc_chan_resources()
2527 dev_err(ud->dev, "Failed to get bcdma irq (index: %u)\n", in bcdma_alloc_chan_resources()
2529 free_irq(uc->irq_num_ring, uc); in bcdma_alloc_chan_resources()
2530 ret = -EINVAL; in bcdma_alloc_chan_resources()
2534 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0, in bcdma_alloc_chan_resources()
2535 uc->name, uc); in bcdma_alloc_chan_resources()
2537 dev_err(ud->dev, "chan%d: BCDMA irq request failed\n", in bcdma_alloc_chan_resources()
2538 uc->id); in bcdma_alloc_chan_resources()
2539 free_irq(uc->irq_num_ring, uc); in bcdma_alloc_chan_resources()
2543 uc->irq_num_udma = 0; in bcdma_alloc_chan_resources()
2548 INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, in bcdma_alloc_chan_resources()
2553 uc->irq_num_ring = 0; in bcdma_alloc_chan_resources()
2554 uc->irq_num_udma = 0; in bcdma_alloc_chan_resources()
2556 if (uc->psil_paired) in bcdma_alloc_chan_resources()
2557 navss_psil_unpair(ud, uc->config.src_thread, in bcdma_alloc_chan_resources()
2558 uc->config.dst_thread); in bcdma_alloc_chan_resources()
2559 uc->psil_paired = false; in bcdma_alloc_chan_resources()
2567 if (uc->use_dma_pool) { in bcdma_alloc_chan_resources()
2568 dma_pool_destroy(uc->hdesc_pool); in bcdma_alloc_chan_resources()
2569 uc->use_dma_pool = false; in bcdma_alloc_chan_resources()
2577 struct k3_event_route_data *router_data = chan->route_data; in bcdma_router_config()
2581 if (!uc->bchan) in bcdma_router_config()
2582 return -EINVAL; in bcdma_router_config()
2584 if (uc->config.tr_trigger_type != 1 && uc->config.tr_trigger_type != 2) in bcdma_router_config()
2585 return -EINVAL; in bcdma_router_config()
2587 trigger_event = uc->ud->soc_data->bcdma_trigger_event_offset; in bcdma_router_config()
2588 trigger_event += (uc->bchan->id * 2) + uc->config.tr_trigger_type - 1; in bcdma_router_config()
2590 return router_data->set_event(router_data->priv, trigger_event); in bcdma_router_config()
2596 struct udma_dev *ud = to_udma_dev(chan->device); in pktdma_alloc_chan_resources()
2597 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in pktdma_alloc_chan_resources()
2605 reinit_completion(&uc->teardown_completed); in pktdma_alloc_chan_resources()
2606 complete_all(&uc->teardown_completed); in pktdma_alloc_chan_resources()
2607 uc->state = UDMA_CHAN_IS_IDLE; in pktdma_alloc_chan_resources()
2609 switch (uc->config.dir) { in pktdma_alloc_chan_resources()
2611 /* Slave transfer synchronized - mem to dev (TX) trasnfer */ in pktdma_alloc_chan_resources()
2612 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, in pktdma_alloc_chan_resources()
2613 uc->id); in pktdma_alloc_chan_resources()
2617 uc->config.remote_thread_id = -1; in pktdma_alloc_chan_resources()
2621 uc->config.src_thread = ud->psil_base + uc->tchan->id; in pktdma_alloc_chan_resources()
2622 uc->config.dst_thread = uc->config.remote_thread_id; in pktdma_alloc_chan_resources()
2623 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; in pktdma_alloc_chan_resources()
2625 irq_ring_idx = uc->tchan->tflow_id + oes->pktdma_tchan_flow; in pktdma_alloc_chan_resources()
2630 /* Slave transfer synchronized - dev to mem (RX) trasnfer */ in pktdma_alloc_chan_resources()
2631 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, in pktdma_alloc_chan_resources()
2632 uc->id); in pktdma_alloc_chan_resources()
2636 uc->config.remote_thread_id = -1; in pktdma_alloc_chan_resources()
2640 uc->config.src_thread = uc->config.remote_thread_id; in pktdma_alloc_chan_resources()
2641 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in pktdma_alloc_chan_resources()
2644 irq_ring_idx = uc->rflow->id + oes->pktdma_rchan_flow; in pktdma_alloc_chan_resources()
2650 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", in pktdma_alloc_chan_resources()
2651 __func__, uc->id, uc->config.dir); in pktdma_alloc_chan_resources()
2652 return -EINVAL; in pktdma_alloc_chan_resources()
2660 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); in pktdma_alloc_chan_resources()
2663 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); in pktdma_alloc_chan_resources()
2664 ret = -EBUSY; in pktdma_alloc_chan_resources()
2669 uc->dma_dev = dmaengine_get_dma_device(chan); in pktdma_alloc_chan_resources()
2670 uc->hdesc_pool = dma_pool_create(uc->name, uc->dma_dev, in pktdma_alloc_chan_resources()
2671 uc->config.hdesc_size, ud->desc_align, in pktdma_alloc_chan_resources()
2673 if (!uc->hdesc_pool) { in pktdma_alloc_chan_resources()
2674 dev_err(ud->ddev.dev, in pktdma_alloc_chan_resources()
2676 uc->use_dma_pool = false; in pktdma_alloc_chan_resources()
2677 ret = -ENOMEM; in pktdma_alloc_chan_resources()
2681 uc->use_dma_pool = true; in pktdma_alloc_chan_resources()
2683 /* PSI-L pairing */ in pktdma_alloc_chan_resources()
2684 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); in pktdma_alloc_chan_resources()
2686 dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", in pktdma_alloc_chan_resources()
2687 uc->config.src_thread, uc->config.dst_thread); in pktdma_alloc_chan_resources()
2691 uc->psil_paired = true; in pktdma_alloc_chan_resources()
2693 uc->irq_num_ring = msi_get_virq(ud->dev, irq_ring_idx); in pktdma_alloc_chan_resources()
2694 if (uc->irq_num_ring <= 0) { in pktdma_alloc_chan_resources()
2695 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n", in pktdma_alloc_chan_resources()
2697 ret = -EINVAL; in pktdma_alloc_chan_resources()
2701 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, in pktdma_alloc_chan_resources()
2702 IRQF_TRIGGER_HIGH, uc->name, uc); in pktdma_alloc_chan_resources()
2704 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); in pktdma_alloc_chan_resources()
2708 uc->irq_num_udma = 0; in pktdma_alloc_chan_resources()
2712 INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, in pktdma_alloc_chan_resources()
2715 if (uc->tchan) in pktdma_alloc_chan_resources()
2716 dev_dbg(ud->dev, in pktdma_alloc_chan_resources()
2718 uc->id, uc->tchan->id, uc->tchan->tflow_id, in pktdma_alloc_chan_resources()
2719 uc->config.remote_thread_id); in pktdma_alloc_chan_resources()
2720 else if (uc->rchan) in pktdma_alloc_chan_resources()
2721 dev_dbg(ud->dev, in pktdma_alloc_chan_resources()
2723 uc->id, uc->rchan->id, uc->rflow->id, in pktdma_alloc_chan_resources()
2724 uc->config.remote_thread_id); in pktdma_alloc_chan_resources()
2728 uc->irq_num_ring = 0; in pktdma_alloc_chan_resources()
2730 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); in pktdma_alloc_chan_resources()
2731 uc->psil_paired = false; in pktdma_alloc_chan_resources()
2738 dma_pool_destroy(uc->hdesc_pool); in pktdma_alloc_chan_resources()
2739 uc->use_dma_pool = false; in pktdma_alloc_chan_resources()
2749 memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); in udma_slave_config()
2771 dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size); in udma_alloc_tr_desc()
2776 d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT); in udma_alloc_tr_desc()
2780 d->sglen = tr_count; in udma_alloc_tr_desc()
2782 d->hwdesc_count = 1; in udma_alloc_tr_desc()
2783 hwdesc = &d->hwdesc[0]; in udma_alloc_tr_desc()
2786 if (uc->use_dma_pool) { in udma_alloc_tr_desc()
2787 hwdesc->cppi5_desc_size = uc->config.hdesc_size; in udma_alloc_tr_desc()
2788 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, in udma_alloc_tr_desc()
2790 &hwdesc->cppi5_desc_paddr); in udma_alloc_tr_desc()
2792 hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, in udma_alloc_tr_desc()
2794 hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, in udma_alloc_tr_desc()
2795 uc->ud->desc_align); in udma_alloc_tr_desc()
2796 hwdesc->cppi5_desc_vaddr = dma_alloc_coherent(uc->ud->dev, in udma_alloc_tr_desc()
2797 hwdesc->cppi5_desc_size, in udma_alloc_tr_desc()
2798 &hwdesc->cppi5_desc_paddr, in udma_alloc_tr_desc()
2802 if (!hwdesc->cppi5_desc_vaddr) { in udma_alloc_tr_desc()
2808 hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; in udma_alloc_tr_desc()
2810 hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size * tr_count; in udma_alloc_tr_desc()
2812 tr_desc = hwdesc->cppi5_desc_vaddr; in udma_alloc_tr_desc()
2814 if (uc->cyclic) in udma_alloc_tr_desc()
2818 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_alloc_tr_desc()
2820 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); in udma_alloc_tr_desc()
2823 cppi5_desc_set_pktids(tr_desc, uc->id, in udma_alloc_tr_desc()
2831 * udma_get_tr_counters - calculate TR counters for a given length
2840 * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1)
2844 * -EINVAL if the length can not be supported
2860 *tr0_cnt0 = SZ_64K - BIT(align_to); in udma_get_tr_counters()
2863 align_to--; in udma_get_tr_counters()
2866 return -EINVAL; in udma_get_tr_counters()
2904 d->sglen = sglen; in udma_prep_slave_sg_tr()
2906 if (uc->ud->match_data->type == DMA_TYPE_UDMA) in udma_prep_slave_sg_tr()
2909 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_slave_sg_tr()
2911 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_tr()
2918 dev_err(uc->ud->dev, "size %u is not supported\n", in udma_prep_slave_sg_tr()
2950 d->residue += sg_dma_len(sgent); in udma_prep_slave_sg_tr()
2953 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_tr()
2980 dev_addr = uc->cfg.src_addr; in udma_prep_slave_sg_triggered_tr()
2981 dev_width = uc->cfg.src_addr_width; in udma_prep_slave_sg_triggered_tr()
2982 burst = uc->cfg.src_maxburst; in udma_prep_slave_sg_triggered_tr()
2983 port_window = uc->cfg.src_port_window_size; in udma_prep_slave_sg_triggered_tr()
2985 dev_addr = uc->cfg.dst_addr; in udma_prep_slave_sg_triggered_tr()
2986 dev_width = uc->cfg.dst_addr_width; in udma_prep_slave_sg_triggered_tr()
2987 burst = uc->cfg.dst_maxburst; in udma_prep_slave_sg_triggered_tr()
2988 port_window = uc->cfg.dst_port_window_size; in udma_prep_slave_sg_triggered_tr()
2990 dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); in udma_prep_slave_sg_triggered_tr()
2999 dev_err(uc->ud->dev, in udma_prep_slave_sg_triggered_tr()
3017 dev_err(uc->ud->dev, in udma_prep_slave_sg_triggered_tr()
3035 d->sglen = sglen; in udma_prep_slave_sg_triggered_tr()
3037 if (uc->ud->match_data->type == DMA_TYPE_UDMA) { in udma_prep_slave_sg_triggered_tr()
3041 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_slave_sg_triggered_tr()
3045 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_triggered_tr()
3054 dev_err(uc->ud->dev, "size %zu is not supported\n", in udma_prep_slave_sg_triggered_tr()
3065 uc->config.tr_trigger_type, in udma_prep_slave_sg_triggered_tr()
3075 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3100 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3111 uc->config.tr_trigger_type, in udma_prep_slave_sg_triggered_tr()
3122 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3145 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3150 d->residue += sg_len; in udma_prep_slave_sg_triggered_tr()
3153 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, csf | CPPI5_TR_CSF_EOP); in udma_prep_slave_sg_triggered_tr()
3162 if (uc->config.ep_type != PSIL_EP_PDMA_XY) in udma_configure_statictr()
3168 d->static_tr.elsize = 0; in udma_configure_statictr()
3171 d->static_tr.elsize = 1; in udma_configure_statictr()
3174 d->static_tr.elsize = 2; in udma_configure_statictr()
3177 d->static_tr.elsize = 3; in udma_configure_statictr()
3180 d->static_tr.elsize = 4; in udma_configure_statictr()
3183 return -EINVAL; in udma_configure_statictr()
3186 d->static_tr.elcnt = elcnt; in udma_configure_statictr()
3188 if (uc->config.pkt_mode || !uc->cyclic) { in udma_configure_statictr()
3197 if (uc->cyclic) in udma_configure_statictr()
3198 d->static_tr.bstcnt = d->residue / d->sglen / div; in udma_configure_statictr()
3200 d->static_tr.bstcnt = d->residue / div; in udma_configure_statictr()
3201 } else if (uc->ud->match_data->type == DMA_TYPE_BCDMA && in udma_configure_statictr()
3202 uc->config.dir == DMA_DEV_TO_MEM && in udma_configure_statictr()
3203 uc->cyclic) { in udma_configure_statictr()
3210 struct cppi5_tr_type1_t *tr_req = d->hwdesc[0].tr_req_base; in udma_configure_statictr()
3212 d->static_tr.bstcnt = in udma_configure_statictr()
3213 (tr_req->icnt0 * tr_req->icnt1) / dev_width; in udma_configure_statictr()
3215 d->static_tr.bstcnt = 0; in udma_configure_statictr()
3218 if (uc->config.dir == DMA_DEV_TO_MEM && in udma_configure_statictr()
3219 d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) in udma_configure_statictr()
3220 return -EINVAL; in udma_configure_statictr()
3241 d->sglen = sglen; in udma_prep_slave_sg_pkt()
3242 d->hwdesc_count = sglen; in udma_prep_slave_sg_pkt()
3245 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_prep_slave_sg_pkt()
3247 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); in udma_prep_slave_sg_pkt()
3249 if (uc->ud->match_data->type == DMA_TYPE_UDMA) in udma_prep_slave_sg_pkt()
3252 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_slave_sg_pkt()
3255 struct udma_hwdesc *hwdesc = &d->hwdesc[i]; in udma_prep_slave_sg_pkt()
3260 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, in udma_prep_slave_sg_pkt()
3262 &hwdesc->cppi5_desc_paddr); in udma_prep_slave_sg_pkt()
3263 if (!hwdesc->cppi5_desc_vaddr) { in udma_prep_slave_sg_pkt()
3264 dev_err(uc->ud->dev, in udma_prep_slave_sg_pkt()
3272 d->residue += sg_len; in udma_prep_slave_sg_pkt()
3273 hwdesc->cppi5_desc_size = uc->config.hdesc_size; in udma_prep_slave_sg_pkt()
3274 desc = hwdesc->cppi5_desc_vaddr; in udma_prep_slave_sg_pkt()
3279 cppi5_desc_set_pktids(&desc->hdr, uc->id, in udma_prep_slave_sg_pkt()
3281 cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); in udma_prep_slave_sg_pkt()
3284 cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); in udma_prep_slave_sg_pkt()
3294 hwdesc->cppi5_desc_paddr | asel); in udma_prep_slave_sg_pkt()
3296 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA || in udma_prep_slave_sg_pkt()
3301 if (d->residue >= SZ_4M) { in udma_prep_slave_sg_pkt()
3302 dev_err(uc->ud->dev, in udma_prep_slave_sg_pkt()
3304 __func__, d->residue); in udma_prep_slave_sg_pkt()
3310 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_prep_slave_sg_pkt()
3311 cppi5_hdesc_set_pktlen(h_desc, d->residue); in udma_prep_slave_sg_pkt()
3320 struct udma_chan *uc = to_udma_chan(desc->chan); in udma_attach_metadata()
3325 if (!uc->config.pkt_mode || !uc->config.metadata_size) in udma_attach_metadata()
3326 return -ENOTSUPP; in udma_attach_metadata()
3328 if (!data || len > uc->config.metadata_size) in udma_attach_metadata()
3329 return -EINVAL; in udma_attach_metadata()
3331 if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE) in udma_attach_metadata()
3332 return -EINVAL; in udma_attach_metadata()
3334 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_attach_metadata()
3335 if (d->dir == DMA_MEM_TO_DEV) in udma_attach_metadata()
3336 memcpy(h_desc->epib, data, len); in udma_attach_metadata()
3338 if (uc->config.needs_epib) in udma_attach_metadata()
3339 psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; in udma_attach_metadata()
3341 d->metadata = data; in udma_attach_metadata()
3342 d->metadata_size = len; in udma_attach_metadata()
3343 if (uc->config.needs_epib) in udma_attach_metadata()
3356 struct udma_chan *uc = to_udma_chan(desc->chan); in udma_get_metadata_ptr()
3359 if (!uc->config.pkt_mode || !uc->config.metadata_size) in udma_get_metadata_ptr()
3360 return ERR_PTR(-ENOTSUPP); in udma_get_metadata_ptr()
3362 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_get_metadata_ptr()
3364 *max_len = uc->config.metadata_size; in udma_get_metadata_ptr()
3366 *payload_len = cppi5_hdesc_epib_present(&h_desc->hdr) ? in udma_get_metadata_ptr()
3370 return h_desc->epib; in udma_get_metadata_ptr()
3377 struct udma_chan *uc = to_udma_chan(desc->chan); in udma_set_metadata_len()
3382 if (!uc->config.pkt_mode || !uc->config.metadata_size) in udma_set_metadata_len()
3383 return -ENOTSUPP; in udma_set_metadata_len()
3385 if (payload_len > uc->config.metadata_size) in udma_set_metadata_len()
3386 return -EINVAL; in udma_set_metadata_len()
3388 if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE) in udma_set_metadata_len()
3389 return -EINVAL; in udma_set_metadata_len()
3391 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_set_metadata_len()
3393 if (uc->config.needs_epib) { in udma_set_metadata_len()
3394 psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; in udma_set_metadata_len()
3420 if (dir != uc->config.dir && in udma_prep_slave_sg()
3421 (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)) { in udma_prep_slave_sg()
3422 dev_err(chan->device->dev, in udma_prep_slave_sg()
3424 __func__, uc->id, in udma_prep_slave_sg()
3425 dmaengine_get_direction_text(uc->config.dir), in udma_prep_slave_sg()
3431 dev_width = uc->cfg.src_addr_width; in udma_prep_slave_sg()
3432 burst = uc->cfg.src_maxburst; in udma_prep_slave_sg()
3434 dev_width = uc->cfg.dst_addr_width; in udma_prep_slave_sg()
3435 burst = uc->cfg.dst_maxburst; in udma_prep_slave_sg()
3437 dev_err(chan->device->dev, "%s: bad direction?\n", __func__); in udma_prep_slave_sg()
3444 uc->config.tx_flags = tx_flags; in udma_prep_slave_sg()
3446 if (uc->config.pkt_mode) in udma_prep_slave_sg()
3449 else if (is_slave_direction(uc->config.dir)) in udma_prep_slave_sg()
3459 d->dir = dir; in udma_prep_slave_sg()
3460 d->desc_idx = 0; in udma_prep_slave_sg()
3461 d->tr_idx = 0; in udma_prep_slave_sg()
3465 dev_err(uc->ud->dev, in udma_prep_slave_sg()
3467 __func__, uc->ud->match_data->statictr_z_mask, in udma_prep_slave_sg()
3468 d->static_tr.bstcnt); in udma_prep_slave_sg()
3475 if (uc->config.metadata_size) in udma_prep_slave_sg()
3476 d->vd.tx.metadata_ops = &metadata_ops; in udma_prep_slave_sg()
3478 return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); in udma_prep_slave_sg()
3498 dev_err(uc->ud->dev, "size %zu is not supported\n", in udma_prep_dma_cyclic_tr()
3509 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_cyclic_tr()
3510 if (uc->ud->match_data->type == DMA_TYPE_UDMA) in udma_prep_dma_cyclic_tr()
3514 ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT); in udma_prep_dma_cyclic_tr()
3517 * For BCDMA <-> PDMA transfers, the EOP flag needs to be set on the in udma_prep_dma_cyclic_tr()
3520 * of TX, and to avoid short-packet error in case of RX. in udma_prep_dma_cyclic_tr()
3525 if (uc->config.ep_type == PSIL_EP_PDMA_XY && in udma_prep_dma_cyclic_tr()
3526 uc->ud->match_data->type == DMA_TYPE_BCDMA) { in udma_prep_dma_cyclic_tr()
3578 if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1)) in udma_prep_dma_cyclic_pkt()
3588 d->hwdesc_count = periods; in udma_prep_dma_cyclic_pkt()
3590 /* TODO: re-check this... */ in udma_prep_dma_cyclic_pkt()
3592 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_prep_dma_cyclic_pkt()
3594 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); in udma_prep_dma_cyclic_pkt()
3596 if (uc->ud->match_data->type != DMA_TYPE_UDMA) in udma_prep_dma_cyclic_pkt()
3597 buf_addr |= (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_dma_cyclic_pkt()
3600 struct udma_hwdesc *hwdesc = &d->hwdesc[i]; in udma_prep_dma_cyclic_pkt()
3604 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, in udma_prep_dma_cyclic_pkt()
3606 &hwdesc->cppi5_desc_paddr); in udma_prep_dma_cyclic_pkt()
3607 if (!hwdesc->cppi5_desc_vaddr) { in udma_prep_dma_cyclic_pkt()
3608 dev_err(uc->ud->dev, in udma_prep_dma_cyclic_pkt()
3616 hwdesc->cppi5_desc_size = uc->config.hdesc_size; in udma_prep_dma_cyclic_pkt()
3617 h_desc = hwdesc->cppi5_desc_vaddr; in udma_prep_dma_cyclic_pkt()
3623 cppi5_desc_set_pktids(&h_desc->hdr, uc->id, in udma_prep_dma_cyclic_pkt()
3625 cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); in udma_prep_dma_cyclic_pkt()
3646 if (dir != uc->config.dir) { in udma_prep_dma_cyclic()
3647 dev_err(chan->device->dev, in udma_prep_dma_cyclic()
3649 __func__, uc->id, in udma_prep_dma_cyclic()
3650 dmaengine_get_direction_text(uc->config.dir), in udma_prep_dma_cyclic()
3655 uc->cyclic = true; in udma_prep_dma_cyclic()
3658 dev_width = uc->cfg.src_addr_width; in udma_prep_dma_cyclic()
3659 burst = uc->cfg.src_maxburst; in udma_prep_dma_cyclic()
3661 dev_width = uc->cfg.dst_addr_width; in udma_prep_dma_cyclic()
3662 burst = uc->cfg.dst_maxburst; in udma_prep_dma_cyclic()
3664 dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); in udma_prep_dma_cyclic()
3671 if (uc->config.pkt_mode) in udma_prep_dma_cyclic()
3681 d->sglen = buf_len / period_len; in udma_prep_dma_cyclic()
3683 d->dir = dir; in udma_prep_dma_cyclic()
3684 d->residue = buf_len; in udma_prep_dma_cyclic()
3688 dev_err(uc->ud->dev, in udma_prep_dma_cyclic()
3690 __func__, uc->ud->match_data->statictr_z_mask, in udma_prep_dma_cyclic()
3691 d->static_tr.bstcnt); in udma_prep_dma_cyclic()
3698 if (uc->config.metadata_size) in udma_prep_dma_cyclic()
3699 d->vd.tx.metadata_ops = &metadata_ops; in udma_prep_dma_cyclic()
3701 return vchan_tx_prep(&uc->vc, &d->vd, flags); in udma_prep_dma_cyclic()
3716 if (uc->config.dir != DMA_MEM_TO_MEM) { in udma_prep_dma_memcpy()
3717 dev_err(chan->device->dev, in udma_prep_dma_memcpy()
3719 __func__, uc->id, in udma_prep_dma_memcpy()
3720 dmaengine_get_direction_text(uc->config.dir), in udma_prep_dma_memcpy()
3728 dev_err(uc->ud->dev, "size %zu is not supported\n", in udma_prep_dma_memcpy()
3737 d->dir = DMA_MEM_TO_MEM; in udma_prep_dma_memcpy()
3738 d->desc_idx = 0; in udma_prep_dma_memcpy()
3739 d->tr_idx = 0; in udma_prep_dma_memcpy()
3740 d->residue = len; in udma_prep_dma_memcpy()
3742 if (uc->ud->match_data->type != DMA_TYPE_UDMA) { in udma_prep_dma_memcpy()
3743 src |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_dma_memcpy()
3744 dest |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_dma_memcpy()
3749 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_memcpy()
3787 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, csf | CPPI5_TR_CSF_EOP); in udma_prep_dma_memcpy()
3789 if (uc->config.metadata_size) in udma_prep_dma_memcpy()
3790 d->vd.tx.metadata_ops = &metadata_ops; in udma_prep_dma_memcpy()
3792 return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); in udma_prep_dma_memcpy()
3800 spin_lock_irqsave(&uc->vc.lock, flags); in udma_issue_pending()
3803 if (vchan_issue_pending(&uc->vc) && !uc->desc) { in udma_issue_pending()
3809 if (!(uc->state == UDMA_CHAN_IS_TERMINATING && in udma_issue_pending()
3814 spin_unlock_irqrestore(&uc->vc.lock, flags); in udma_issue_pending()
3825 spin_lock_irqsave(&uc->vc.lock, flags); in udma_tx_status()
3838 if (uc->desc && uc->desc->vd.tx.cookie == cookie) { in udma_tx_status()
3841 u32 residue = uc->desc->residue; in udma_tx_status()
3844 if (uc->desc->dir == DMA_MEM_TO_DEV) { in udma_tx_status()
3847 if (uc->config.ep_type != PSIL_EP_NATIVE) { in udma_tx_status()
3852 delay = bcnt - peer_bcnt; in udma_tx_status()
3854 } else if (uc->desc->dir == DMA_DEV_TO_MEM) { in udma_tx_status()
3857 if (uc->config.ep_type != PSIL_EP_NATIVE) { in udma_tx_status()
3862 delay = peer_bcnt - bcnt; in udma_tx_status()
3868 if (bcnt && !(bcnt % uc->desc->residue)) in udma_tx_status()
3871 residue -= bcnt % uc->desc->residue; in udma_tx_status()
3873 if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) { in udma_tx_status()
3886 spin_unlock_irqrestore(&uc->vc.lock, flags); in udma_tx_status()
3895 switch (uc->config.dir) { in udma_pause()
3912 return -EINVAL; in udma_pause()
3923 switch (uc->config.dir) { in udma_resume()
3938 return -EINVAL; in udma_resume()
3950 spin_lock_irqsave(&uc->vc.lock, flags); in udma_terminate_all()
3955 if (uc->desc) { in udma_terminate_all()
3956 uc->terminated_desc = uc->desc; in udma_terminate_all()
3957 uc->desc = NULL; in udma_terminate_all()
3958 uc->terminated_desc->terminated = true; in udma_terminate_all()
3959 cancel_delayed_work(&uc->tx_drain.work); in udma_terminate_all()
3962 uc->paused = false; in udma_terminate_all()
3964 vchan_get_all_descriptors(&uc->vc, &head); in udma_terminate_all()
3965 spin_unlock_irqrestore(&uc->vc.lock, flags); in udma_terminate_all()
3966 vchan_dma_desc_free_list(&uc->vc, &head); in udma_terminate_all()
3976 vchan_synchronize(&uc->vc); in udma_synchronize()
3978 if (uc->state == UDMA_CHAN_IS_TERMINATING) { in udma_synchronize()
3979 timeout = wait_for_completion_timeout(&uc->teardown_completed, in udma_synchronize()
3982 dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", in udma_synchronize()
3983 uc->id); in udma_synchronize()
3991 dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); in udma_synchronize()
3993 cancel_delayed_work_sync(&uc->tx_drain.work); in udma_synchronize()
4001 struct udma_chan *uc = to_udma_chan(&vc->chan); in udma_desc_pre_callback()
4008 d = to_udma_desc(&vd->tx); in udma_desc_pre_callback()
4010 if (d->metadata_size) in udma_desc_pre_callback()
4014 void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx); in udma_desc_pre_callback()
4019 result->residue = d->residue - in udma_desc_pre_callback()
4021 if (result->residue) in udma_desc_pre_callback()
4022 result->result = DMA_TRANS_ABORTED; in udma_desc_pre_callback()
4024 result->result = DMA_TRANS_NOERROR; in udma_desc_pre_callback()
4026 result->residue = 0; in udma_desc_pre_callback()
4028 status = d->hwdesc[0].tr_resp_base->status; in udma_desc_pre_callback()
4030 result->result = DMA_TRANS_ABORTED; in udma_desc_pre_callback()
4032 result->result = DMA_TRANS_NOERROR; in udma_desc_pre_callback()
4048 spin_lock_irq(&vc->lock); in udma_vchan_complete()
4049 list_splice_tail_init(&vc->desc_completed, &head); in udma_vchan_complete()
4050 vd = vc->cyclic; in udma_vchan_complete()
4052 vc->cyclic = NULL; in udma_vchan_complete()
4053 dmaengine_desc_get_callback(&vd->tx, &cb); in udma_vchan_complete()
4057 spin_unlock_irq(&vc->lock); in udma_vchan_complete()
4065 dmaengine_desc_get_callback(&vd->tx, &cb); in udma_vchan_complete()
4067 list_del(&vd->node); in udma_vchan_complete()
4079 struct udma_dev *ud = to_udma_dev(chan->device); in udma_free_chan_resources()
4082 if (uc->terminated_desc) { in udma_free_chan_resources()
4087 cancel_delayed_work_sync(&uc->tx_drain.work); in udma_free_chan_resources()
4089 if (uc->irq_num_ring > 0) { in udma_free_chan_resources()
4090 free_irq(uc->irq_num_ring, uc); in udma_free_chan_resources()
4092 uc->irq_num_ring = 0; in udma_free_chan_resources()
4094 if (uc->irq_num_udma > 0) { in udma_free_chan_resources()
4095 free_irq(uc->irq_num_udma, uc); in udma_free_chan_resources()
4097 uc->irq_num_udma = 0; in udma_free_chan_resources()
4100 /* Release PSI-L pairing */ in udma_free_chan_resources()
4101 if (uc->psil_paired) { in udma_free_chan_resources()
4102 navss_psil_unpair(ud, uc->config.src_thread, in udma_free_chan_resources()
4103 uc->config.dst_thread); in udma_free_chan_resources()
4104 uc->psil_paired = false; in udma_free_chan_resources()
4107 vchan_free_chan_resources(&uc->vc); in udma_free_chan_resources()
4108 tasklet_kill(&uc->vc.task); in udma_free_chan_resources()
4115 if (uc->use_dma_pool) { in udma_free_chan_resources()
4116 dma_pool_destroy(uc->hdesc_pool); in udma_free_chan_resources()
4117 uc->use_dma_pool = false; in udma_free_chan_resources()
4140 if (chan->device->dev->driver != &udma_driver.driver && in udma_dma_filter_fn()
4141 chan->device->dev->driver != &bcdma_driver.driver && in udma_dma_filter_fn()
4142 chan->device->dev->driver != &pktdma_driver.driver) in udma_dma_filter_fn()
4146 ucc = &uc->config; in udma_dma_filter_fn()
4147 ud = uc->ud; in udma_dma_filter_fn()
4150 if (filter_param->atype > 2) { in udma_dma_filter_fn()
4151 dev_err(ud->dev, "Invalid channel atype: %u\n", in udma_dma_filter_fn()
4152 filter_param->atype); in udma_dma_filter_fn()
4156 if (filter_param->asel > 15) { in udma_dma_filter_fn()
4157 dev_err(ud->dev, "Invalid channel asel: %u\n", in udma_dma_filter_fn()
4158 filter_param->asel); in udma_dma_filter_fn()
4162 ucc->remote_thread_id = filter_param->remote_thread_id; in udma_dma_filter_fn()
4163 ucc->atype = filter_param->atype; in udma_dma_filter_fn()
4164 ucc->asel = filter_param->asel; in udma_dma_filter_fn()
4165 ucc->tr_trigger_type = filter_param->tr_trigger_type; in udma_dma_filter_fn()
4167 if (ucc->tr_trigger_type) { in udma_dma_filter_fn()
4168 ucc->dir = DMA_MEM_TO_MEM; in udma_dma_filter_fn()
4170 } else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) { in udma_dma_filter_fn()
4171 ucc->dir = DMA_MEM_TO_DEV; in udma_dma_filter_fn()
4173 ucc->dir = DMA_DEV_TO_MEM; in udma_dma_filter_fn()
4176 ep_config = psil_get_ep_config(ucc->remote_thread_id); in udma_dma_filter_fn()
4178 dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n", in udma_dma_filter_fn()
4179 ucc->remote_thread_id); in udma_dma_filter_fn()
4180 ucc->dir = DMA_MEM_TO_MEM; in udma_dma_filter_fn()
4181 ucc->remote_thread_id = -1; in udma_dma_filter_fn()
4182 ucc->atype = 0; in udma_dma_filter_fn()
4183 ucc->asel = 0; in udma_dma_filter_fn()
4187 if (ud->match_data->type == DMA_TYPE_BCDMA && in udma_dma_filter_fn()
4188 ep_config->pkt_mode) { in udma_dma_filter_fn()
4189 dev_err(ud->dev, in udma_dma_filter_fn()
4190 "Only TR mode is supported (psi-l thread 0x%04x)\n", in udma_dma_filter_fn()
4191 ucc->remote_thread_id); in udma_dma_filter_fn()
4192 ucc->dir = DMA_MEM_TO_MEM; in udma_dma_filter_fn()
4193 ucc->remote_thread_id = -1; in udma_dma_filter_fn()
4194 ucc->atype = 0; in udma_dma_filter_fn()
4195 ucc->asel = 0; in udma_dma_filter_fn()
4199 ucc->pkt_mode = ep_config->pkt_mode; in udma_dma_filter_fn()
4200 ucc->channel_tpl = ep_config->channel_tpl; in udma_dma_filter_fn()
4201 ucc->notdpkt = ep_config->notdpkt; in udma_dma_filter_fn()
4202 ucc->ep_type = ep_config->ep_type; in udma_dma_filter_fn()
4204 if (ud->match_data->type == DMA_TYPE_PKTDMA && in udma_dma_filter_fn()
4205 ep_config->mapped_channel_id >= 0) { in udma_dma_filter_fn()
4206 ucc->mapped_channel_id = ep_config->mapped_channel_id; in udma_dma_filter_fn()
4207 ucc->default_flow_id = ep_config->default_flow_id; in udma_dma_filter_fn()
4209 ucc->mapped_channel_id = -1; in udma_dma_filter_fn()
4210 ucc->default_flow_id = -1; in udma_dma_filter_fn()
4213 if (ucc->ep_type != PSIL_EP_NATIVE) { in udma_dma_filter_fn()
4214 const struct udma_match_data *match_data = ud->match_data; in udma_dma_filter_fn()
4216 if (match_data->flags & UDMA_FLAG_PDMA_ACC32) in udma_dma_filter_fn()
4217 ucc->enable_acc32 = ep_config->pdma_acc32; in udma_dma_filter_fn()
4218 if (match_data->flags & UDMA_FLAG_PDMA_BURST) in udma_dma_filter_fn()
4219 ucc->enable_burst = ep_config->pdma_burst; in udma_dma_filter_fn()
4222 ucc->needs_epib = ep_config->needs_epib; in udma_dma_filter_fn()
4223 ucc->psd_size = ep_config->psd_size; in udma_dma_filter_fn()
4224 ucc->metadata_size = in udma_dma_filter_fn()
4225 (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + in udma_dma_filter_fn()
4226 ucc->psd_size; in udma_dma_filter_fn()
4228 if (ucc->pkt_mode) in udma_dma_filter_fn()
4229 ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + in udma_dma_filter_fn()
4230 ucc->metadata_size, ud->desc_align); in udma_dma_filter_fn()
4232 dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id, in udma_dma_filter_fn()
4233 ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir)); in udma_dma_filter_fn()
4238 dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id, in udma_dma_filter_fn()
4239 ucc->tr_trigger_type); in udma_dma_filter_fn()
4248 struct udma_dev *ud = ofdma->of_dma_data; in udma_of_xlate()
4249 dma_cap_mask_t mask = ud->ddev.cap_mask; in udma_of_xlate()
4253 if (ud->match_data->type == DMA_TYPE_BCDMA) { in udma_of_xlate()
4254 if (dma_spec->args_count != 3) in udma_of_xlate()
4257 filter_param.tr_trigger_type = dma_spec->args[0]; in udma_of_xlate()
4258 filter_param.remote_thread_id = dma_spec->args[1]; in udma_of_xlate()
4259 filter_param.asel = dma_spec->args[2]; in udma_of_xlate()
4262 if (dma_spec->args_count != 1 && dma_spec->args_count != 2) in udma_of_xlate()
4265 filter_param.remote_thread_id = dma_spec->args[0]; in udma_of_xlate()
4267 if (dma_spec->args_count == 2) { in udma_of_xlate()
4268 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_of_xlate()
4269 filter_param.atype = dma_spec->args[1]; in udma_of_xlate()
4273 filter_param.asel = dma_spec->args[1]; in udma_of_xlate()
4282 ofdma->of_node); in udma_of_xlate()
4284 dev_err(ud->dev, "get channel fail in %s.\n", __func__); in udma_of_xlate()
4285 return ERR_PTR(-EINVAL); in udma_of_xlate()
4385 .enable_memcpy_support = false, /* PKTDMA does not support MEM_TO_MEM */
4409 .compatible = "ti,am654-navss-main-udmap",
4413 .compatible = "ti,am654-navss-mcu-udmap",
4416 .compatible = "ti,j721e-navss-main-udmap",
4419 .compatible = "ti,j721e-navss-mcu-udmap",
4423 .compatible = "ti,am64-dmss-bcdma",
4427 .compatible = "ti,am64-dmss-pktdma",
4431 .compatible = "ti,am62a-dmss-bcdma-csirx",
4435 .compatible = "ti,j721s2-dmss-bcdma-csi",
4493 ud->mmrs[MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev, mmr_names[MMR_GCFG]); in udma_get_mmrs()
4494 if (IS_ERR(ud->mmrs[MMR_GCFG])) in udma_get_mmrs()
4495 return PTR_ERR(ud->mmrs[MMR_GCFG]); in udma_get_mmrs()
4497 cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); in udma_get_mmrs()
4498 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in udma_get_mmrs()
4500 switch (ud->match_data->type) { in udma_get_mmrs()
4502 ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3); in udma_get_mmrs()
4503 ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2); in udma_get_mmrs()
4504 ud->echan_cnt = UDMA_CAP2_ECHAN_CNT(cap2); in udma_get_mmrs()
4505 ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2); in udma_get_mmrs()
4508 ud->bchan_cnt = BCDMA_CAP2_BCHAN_CNT(cap2) + in udma_get_mmrs()
4511 ud->tchan_cnt = BCDMA_CAP2_TCHAN_CNT(cap2); in udma_get_mmrs()
4512 ud->rchan_cnt = BCDMA_CAP2_RCHAN_CNT(cap2); in udma_get_mmrs()
4513 ud->rflow_cnt = ud->rchan_cnt; in udma_get_mmrs()
4516 cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30); in udma_get_mmrs()
4517 ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2); in udma_get_mmrs()
4518 ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2); in udma_get_mmrs()
4519 ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3); in udma_get_mmrs()
4520 ud->tflow_cnt = PKTDMA_CAP4_TFLOW_CNT(cap4); in udma_get_mmrs()
4523 return -EINVAL; in udma_get_mmrs()
4527 if (i == MMR_BCHANRT && ud->bchan_cnt == 0) in udma_get_mmrs()
4529 if (i == MMR_TCHANRT && ud->tchan_cnt == 0) in udma_get_mmrs()
4531 if (i == MMR_RCHANRT && ud->rchan_cnt == 0) in udma_get_mmrs()
4534 ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, mmr_names[i]); in udma_get_mmrs()
4535 if (IS_ERR(ud->mmrs[i])) in udma_get_mmrs()
4536 return PTR_ERR(ud->mmrs[i]); in udma_get_mmrs()
4546 bitmap_clear(map, rm_desc->start, rm_desc->num); in udma_mark_resource_ranges()
4547 bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec); in udma_mark_resource_ranges()
4548 dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name, in udma_mark_resource_ranges()
4549 rm_desc->start, rm_desc->num, rm_desc->start_sec, in udma_mark_resource_ranges()
4550 rm_desc->num_sec); in udma_mark_resource_ranges()
4554 [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
4555 [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
4556 [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
4557 [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
4558 [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
4564 struct device *dev = ud->dev; in udma_setup_resources()
4566 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_setup_resources()
4570 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in udma_setup_resources()
4571 if (of_device_is_compatible(dev->of_node, in udma_setup_resources()
4572 "ti,am654-navss-main-udmap")) { in udma_setup_resources()
4573 ud->tchan_tpl.levels = 2; in udma_setup_resources()
4574 ud->tchan_tpl.start_idx[0] = 8; in udma_setup_resources()
4575 } else if (of_device_is_compatible(dev->of_node, in udma_setup_resources()
4576 "ti,am654-navss-mcu-udmap")) { in udma_setup_resources()
4577 ud->tchan_tpl.levels = 2; in udma_setup_resources()
4578 ud->tchan_tpl.start_idx[0] = 2; in udma_setup_resources()
4580 ud->tchan_tpl.levels = 3; in udma_setup_resources()
4581 ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); in udma_setup_resources()
4582 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in udma_setup_resources()
4584 ud->tchan_tpl.levels = 2; in udma_setup_resources()
4585 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in udma_setup_resources()
4587 ud->tchan_tpl.levels = 1; in udma_setup_resources()
4590 ud->rchan_tpl.levels = ud->tchan_tpl.levels; in udma_setup_resources()
4591 ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; in udma_setup_resources()
4592 ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; in udma_setup_resources()
4594 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), in udma_setup_resources()
4596 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), in udma_setup_resources()
4598 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), in udma_setup_resources()
4600 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), in udma_setup_resources()
4602 ud->rflow_gp_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt), in udma_setup_resources()
4605 ud->rflow_gp_map_allocated = devm_kcalloc(dev, in udma_setup_resources()
4606 BITS_TO_LONGS(ud->rflow_cnt), in udma_setup_resources()
4609 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), in udma_setup_resources()
4612 ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), in udma_setup_resources()
4615 if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_gp_map || in udma_setup_resources()
4616 !ud->rflow_gp_map_allocated || !ud->tchans || !ud->rchans || in udma_setup_resources()
4617 !ud->rflows || !ud->rflow_in_use) in udma_setup_resources()
4618 return -ENOMEM; in udma_setup_resources()
4625 bitmap_set(ud->rflow_gp_map_allocated, 0, ud->rchan_cnt); in udma_setup_resources()
4628 bitmap_set(ud->rflow_gp_map, 0, ud->rflow_cnt); in udma_setup_resources()
4635 tisci_rm->rm_ranges[i] = in udma_setup_resources()
4636 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, in udma_setup_resources()
4637 tisci_rm->tisci_dev_id, in udma_setup_resources()
4642 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in udma_setup_resources()
4644 bitmap_zero(ud->tchan_map, ud->tchan_cnt); in udma_setup_resources()
4647 bitmap_fill(ud->tchan_map, ud->tchan_cnt); in udma_setup_resources()
4648 for (i = 0; i < rm_res->sets; i++) in udma_setup_resources()
4649 udma_mark_resource_ranges(ud, ud->tchan_map, in udma_setup_resources()
4650 &rm_res->desc[i], "tchan"); in udma_setup_resources()
4651 irq_res.sets = rm_res->sets; in udma_setup_resources()
4655 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in udma_setup_resources()
4657 bitmap_zero(ud->rchan_map, ud->rchan_cnt); in udma_setup_resources()
4660 bitmap_fill(ud->rchan_map, ud->rchan_cnt); in udma_setup_resources()
4661 for (i = 0; i < rm_res->sets; i++) in udma_setup_resources()
4662 udma_mark_resource_ranges(ud, ud->rchan_map, in udma_setup_resources()
4663 &rm_res->desc[i], "rchan"); in udma_setup_resources()
4664 irq_res.sets += rm_res->sets; in udma_setup_resources()
4669 return -ENOMEM; in udma_setup_resources()
4670 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in udma_setup_resources()
4673 irq_res.desc[0].num = ud->tchan_cnt; in udma_setup_resources()
4676 for (i = 0; i < rm_res->sets; i++) { in udma_setup_resources()
4677 irq_res.desc[i].start = rm_res->desc[i].start; in udma_setup_resources()
4678 irq_res.desc[i].num = rm_res->desc[i].num; in udma_setup_resources()
4679 irq_res.desc[i].start_sec = rm_res->desc[i].start_sec; in udma_setup_resources()
4680 irq_res.desc[i].num_sec = rm_res->desc[i].num_sec; in udma_setup_resources()
4683 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in udma_setup_resources()
4686 irq_res.desc[i].num = ud->rchan_cnt; in udma_setup_resources()
4688 for (j = 0; j < rm_res->sets; j++, i++) { in udma_setup_resources()
4689 if (rm_res->desc[j].num) { in udma_setup_resources()
4690 irq_res.desc[i].start = rm_res->desc[j].start + in udma_setup_resources()
4691 ud->soc_data->oes.udma_rchan; in udma_setup_resources()
4692 irq_res.desc[i].num = rm_res->desc[j].num; in udma_setup_resources()
4694 if (rm_res->desc[j].num_sec) { in udma_setup_resources()
4695 irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + in udma_setup_resources()
4696 ud->soc_data->oes.udma_rchan; in udma_setup_resources()
4697 irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; in udma_setup_resources()
4701 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); in udma_setup_resources()
4704 dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); in udma_setup_resources()
4709 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; in udma_setup_resources()
4712 bitmap_clear(ud->rflow_gp_map, ud->rchan_cnt, in udma_setup_resources()
4713 ud->rflow_cnt - ud->rchan_cnt); in udma_setup_resources()
4715 for (i = 0; i < rm_res->sets; i++) in udma_setup_resources()
4716 udma_mark_resource_ranges(ud, ud->rflow_gp_map, in udma_setup_resources()
4717 &rm_res->desc[i], "gp-rflow"); in udma_setup_resources()
4726 struct device *dev = ud->dev; in bcdma_setup_resources()
4728 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_setup_resources()
4729 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in bcdma_setup_resources()
4733 cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in bcdma_setup_resources()
4735 ud->bchan_tpl.levels = 3; in bcdma_setup_resources()
4736 ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap); in bcdma_setup_resources()
4737 ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); in bcdma_setup_resources()
4739 ud->bchan_tpl.levels = 2; in bcdma_setup_resources()
4740 ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); in bcdma_setup_resources()
4742 ud->bchan_tpl.levels = 1; in bcdma_setup_resources()
4745 cap = udma_read(ud->mmrs[MMR_GCFG], 0x30); in bcdma_setup_resources()
4747 ud->rchan_tpl.levels = 3; in bcdma_setup_resources()
4748 ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap); in bcdma_setup_resources()
4749 ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); in bcdma_setup_resources()
4751 ud->rchan_tpl.levels = 2; in bcdma_setup_resources()
4752 ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); in bcdma_setup_resources()
4754 ud->rchan_tpl.levels = 1; in bcdma_setup_resources()
4758 ud->tchan_tpl.levels = 3; in bcdma_setup_resources()
4759 ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap); in bcdma_setup_resources()
4760 ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); in bcdma_setup_resources()
4762 ud->tchan_tpl.levels = 2; in bcdma_setup_resources()
4763 ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); in bcdma_setup_resources()
4765 ud->tchan_tpl.levels = 1; in bcdma_setup_resources()
4768 ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt), in bcdma_setup_resources()
4770 ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans), in bcdma_setup_resources()
4772 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), in bcdma_setup_resources()
4774 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), in bcdma_setup_resources()
4776 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), in bcdma_setup_resources()
4778 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), in bcdma_setup_resources()
4781 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), in bcdma_setup_resources()
4784 ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), in bcdma_setup_resources()
4787 if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || in bcdma_setup_resources()
4788 !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || in bcdma_setup_resources()
4789 !ud->rflows) in bcdma_setup_resources()
4790 return -ENOMEM; in bcdma_setup_resources()
4796 if (i == RM_RANGE_BCHAN && ud->bchan_cnt == 0) in bcdma_setup_resources()
4798 if (i == RM_RANGE_TCHAN && ud->tchan_cnt == 0) in bcdma_setup_resources()
4800 if (i == RM_RANGE_RCHAN && ud->rchan_cnt == 0) in bcdma_setup_resources()
4803 tisci_rm->rm_ranges[i] = in bcdma_setup_resources()
4804 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, in bcdma_setup_resources()
4805 tisci_rm->tisci_dev_id, in bcdma_setup_resources()
4812 if (ud->bchan_cnt) { in bcdma_setup_resources()
4813 rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; in bcdma_setup_resources()
4815 bitmap_zero(ud->bchan_map, ud->bchan_cnt); in bcdma_setup_resources()
4818 bitmap_fill(ud->bchan_map, ud->bchan_cnt); in bcdma_setup_resources()
4819 for (i = 0; i < rm_res->sets; i++) in bcdma_setup_resources()
4820 udma_mark_resource_ranges(ud, ud->bchan_map, in bcdma_setup_resources()
4821 &rm_res->desc[i], in bcdma_setup_resources()
4823 irq_res.sets += rm_res->sets; in bcdma_setup_resources()
4828 if (ud->tchan_cnt) { in bcdma_setup_resources()
4829 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in bcdma_setup_resources()
4831 bitmap_zero(ud->tchan_map, ud->tchan_cnt); in bcdma_setup_resources()
4834 bitmap_fill(ud->tchan_map, ud->tchan_cnt); in bcdma_setup_resources()
4835 for (i = 0; i < rm_res->sets; i++) in bcdma_setup_resources()
4836 udma_mark_resource_ranges(ud, ud->tchan_map, in bcdma_setup_resources()
4837 &rm_res->desc[i], in bcdma_setup_resources()
4839 irq_res.sets += rm_res->sets * 2; in bcdma_setup_resources()
4844 if (ud->rchan_cnt) { in bcdma_setup_resources()
4845 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in bcdma_setup_resources()
4847 bitmap_zero(ud->rchan_map, ud->rchan_cnt); in bcdma_setup_resources()
4850 bitmap_fill(ud->rchan_map, ud->rchan_cnt); in bcdma_setup_resources()
4851 for (i = 0; i < rm_res->sets; i++) in bcdma_setup_resources()
4852 udma_mark_resource_ranges(ud, ud->rchan_map, in bcdma_setup_resources()
4853 &rm_res->desc[i], in bcdma_setup_resources()
4855 irq_res.sets += rm_res->sets * 2; in bcdma_setup_resources()
4861 return -ENOMEM; in bcdma_setup_resources()
4862 if (ud->bchan_cnt) { in bcdma_setup_resources()
4863 rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; in bcdma_setup_resources()
4865 irq_res.desc[0].start = oes->bcdma_bchan_ring; in bcdma_setup_resources()
4866 irq_res.desc[0].num = ud->bchan_cnt; in bcdma_setup_resources()
4869 for (i = 0; i < rm_res->sets; i++) { in bcdma_setup_resources()
4870 irq_res.desc[i].start = rm_res->desc[i].start + in bcdma_setup_resources()
4871 oes->bcdma_bchan_ring; in bcdma_setup_resources()
4872 irq_res.desc[i].num = rm_res->desc[i].num; in bcdma_setup_resources()
4879 if (ud->tchan_cnt) { in bcdma_setup_resources()
4880 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in bcdma_setup_resources()
4882 irq_res.desc[i].start = oes->bcdma_tchan_data; in bcdma_setup_resources()
4883 irq_res.desc[i].num = ud->tchan_cnt; in bcdma_setup_resources()
4884 irq_res.desc[i + 1].start = oes->bcdma_tchan_ring; in bcdma_setup_resources()
4885 irq_res.desc[i + 1].num = ud->tchan_cnt; in bcdma_setup_resources()
4888 for (j = 0; j < rm_res->sets; j++, i += 2) { in bcdma_setup_resources()
4889 irq_res.desc[i].start = rm_res->desc[j].start + in bcdma_setup_resources()
4890 oes->bcdma_tchan_data; in bcdma_setup_resources()
4891 irq_res.desc[i].num = rm_res->desc[j].num; in bcdma_setup_resources()
4893 irq_res.desc[i + 1].start = rm_res->desc[j].start + in bcdma_setup_resources()
4894 oes->bcdma_tchan_ring; in bcdma_setup_resources()
4895 irq_res.desc[i + 1].num = rm_res->desc[j].num; in bcdma_setup_resources()
4899 if (ud->rchan_cnt) { in bcdma_setup_resources()
4900 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in bcdma_setup_resources()
4902 irq_res.desc[i].start = oes->bcdma_rchan_data; in bcdma_setup_resources()
4903 irq_res.desc[i].num = ud->rchan_cnt; in bcdma_setup_resources()
4904 irq_res.desc[i + 1].start = oes->bcdma_rchan_ring; in bcdma_setup_resources()
4905 irq_res.desc[i + 1].num = ud->rchan_cnt; in bcdma_setup_resources()
4908 for (j = 0; j < rm_res->sets; j++, i += 2) { in bcdma_setup_resources()
4909 irq_res.desc[i].start = rm_res->desc[j].start + in bcdma_setup_resources()
4910 oes->bcdma_rchan_data; in bcdma_setup_resources()
4911 irq_res.desc[i].num = rm_res->desc[j].num; in bcdma_setup_resources()
4913 irq_res.desc[i + 1].start = rm_res->desc[j].start + in bcdma_setup_resources()
4914 oes->bcdma_rchan_ring; in bcdma_setup_resources()
4915 irq_res.desc[i + 1].num = rm_res->desc[j].num; in bcdma_setup_resources()
4920 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); in bcdma_setup_resources()
4923 dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); in bcdma_setup_resources()
4933 struct device *dev = ud->dev; in pktdma_setup_resources()
4935 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in pktdma_setup_resources()
4936 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in pktdma_setup_resources()
4940 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in pktdma_setup_resources()
4942 ud->tchan_tpl.levels = 3; in pktdma_setup_resources()
4943 ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); in pktdma_setup_resources()
4944 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in pktdma_setup_resources()
4946 ud->tchan_tpl.levels = 2; in pktdma_setup_resources()
4947 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in pktdma_setup_resources()
4949 ud->tchan_tpl.levels = 1; in pktdma_setup_resources()
4952 ud->rchan_tpl.levels = ud->tchan_tpl.levels; in pktdma_setup_resources()
4953 ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; in pktdma_setup_resources()
4954 ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; in pktdma_setup_resources()
4956 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), in pktdma_setup_resources()
4958 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), in pktdma_setup_resources()
4960 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), in pktdma_setup_resources()
4962 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), in pktdma_setup_resources()
4964 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), in pktdma_setup_resources()
4967 ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), in pktdma_setup_resources()
4969 ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), in pktdma_setup_resources()
4972 if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || in pktdma_setup_resources()
4973 !ud->rchans || !ud->rflows || !ud->rflow_in_use) in pktdma_setup_resources()
4974 return -ENOMEM; in pktdma_setup_resources()
4981 tisci_rm->rm_ranges[i] = in pktdma_setup_resources()
4982 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, in pktdma_setup_resources()
4983 tisci_rm->tisci_dev_id, in pktdma_setup_resources()
4988 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in pktdma_setup_resources()
4990 bitmap_zero(ud->tchan_map, ud->tchan_cnt); in pktdma_setup_resources()
4992 bitmap_fill(ud->tchan_map, ud->tchan_cnt); in pktdma_setup_resources()
4993 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
4994 udma_mark_resource_ranges(ud, ud->tchan_map, in pktdma_setup_resources()
4995 &rm_res->desc[i], "tchan"); in pktdma_setup_resources()
4999 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in pktdma_setup_resources()
5001 bitmap_zero(ud->rchan_map, ud->rchan_cnt); in pktdma_setup_resources()
5003 bitmap_fill(ud->rchan_map, ud->rchan_cnt); in pktdma_setup_resources()
5004 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
5005 udma_mark_resource_ranges(ud, ud->rchan_map, in pktdma_setup_resources()
5006 &rm_res->desc[i], "rchan"); in pktdma_setup_resources()
5010 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; in pktdma_setup_resources()
5013 bitmap_zero(ud->rflow_in_use, ud->rflow_cnt); in pktdma_setup_resources()
5016 bitmap_fill(ud->rflow_in_use, ud->rflow_cnt); in pktdma_setup_resources()
5017 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
5018 udma_mark_resource_ranges(ud, ud->rflow_in_use, in pktdma_setup_resources()
5019 &rm_res->desc[i], "rflow"); in pktdma_setup_resources()
5020 irq_res.sets = rm_res->sets; in pktdma_setup_resources()
5024 rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; in pktdma_setup_resources()
5027 bitmap_zero(ud->tflow_map, ud->tflow_cnt); in pktdma_setup_resources()
5030 bitmap_fill(ud->tflow_map, ud->tflow_cnt); in pktdma_setup_resources()
5031 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
5032 udma_mark_resource_ranges(ud, ud->tflow_map, in pktdma_setup_resources()
5033 &rm_res->desc[i], "tflow"); in pktdma_setup_resources()
5034 irq_res.sets += rm_res->sets; in pktdma_setup_resources()
5039 return -ENOMEM; in pktdma_setup_resources()
5040 rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; in pktdma_setup_resources()
5042 irq_res.desc[0].start = oes->pktdma_tchan_flow; in pktdma_setup_resources()
5043 irq_res.desc[0].num = ud->tflow_cnt; in pktdma_setup_resources()
5046 for (i = 0; i < rm_res->sets; i++) { in pktdma_setup_resources()
5047 irq_res.desc[i].start = rm_res->desc[i].start + in pktdma_setup_resources()
5048 oes->pktdma_tchan_flow; in pktdma_setup_resources()
5049 irq_res.desc[i].num = rm_res->desc[i].num; in pktdma_setup_resources()
5052 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; in pktdma_setup_resources()
5054 irq_res.desc[i].start = oes->pktdma_rchan_flow; in pktdma_setup_resources()
5055 irq_res.desc[i].num = ud->rflow_cnt; in pktdma_setup_resources()
5057 for (j = 0; j < rm_res->sets; j++, i++) { in pktdma_setup_resources()
5058 irq_res.desc[i].start = rm_res->desc[j].start + in pktdma_setup_resources()
5059 oes->pktdma_rchan_flow; in pktdma_setup_resources()
5060 irq_res.desc[i].num = rm_res->desc[j].num; in pktdma_setup_resources()
5063 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); in pktdma_setup_resources()
5066 dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); in pktdma_setup_resources()
5075 struct device *dev = ud->dev; in setup_resources()
5078 switch (ud->match_data->type) { in setup_resources()
5089 return -EINVAL; in setup_resources()
5095 ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; in setup_resources()
5096 if (ud->bchan_cnt) in setup_resources()
5097 ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt); in setup_resources()
5098 ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); in setup_resources()
5099 ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); in setup_resources()
5101 return -ENODEV; in setup_resources()
5103 ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), in setup_resources()
5105 if (!ud->channels) in setup_resources()
5106 return -ENOMEM; in setup_resources()
5108 switch (ud->match_data->type) { in setup_resources()
5111 "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n", in setup_resources()
5113 ud->tchan_cnt - bitmap_weight(ud->tchan_map, in setup_resources()
5114 ud->tchan_cnt), in setup_resources()
5115 ud->rchan_cnt - bitmap_weight(ud->rchan_map, in setup_resources()
5116 ud->rchan_cnt), in setup_resources()
5117 ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, in setup_resources()
5118 ud->rflow_cnt)); in setup_resources()
5124 ud->bchan_cnt - bitmap_weight(ud->bchan_map, in setup_resources()
5125 ud->bchan_cnt), in setup_resources()
5126 ud->tchan_cnt - bitmap_weight(ud->tchan_map, in setup_resources()
5127 ud->tchan_cnt), in setup_resources()
5128 ud->rchan_cnt - bitmap_weight(ud->rchan_map, in setup_resources()
5129 ud->rchan_cnt)); in setup_resources()
5135 ud->tchan_cnt - bitmap_weight(ud->tchan_map, in setup_resources()
5136 ud->tchan_cnt), in setup_resources()
5137 ud->rchan_cnt - bitmap_weight(ud->rchan_map, in setup_resources()
5138 ud->rchan_cnt)); in setup_resources()
5149 struct udma_rx_flush *rx_flush = &ud->rx_flush; in udma_setup_rx_flush()
5153 struct device *dev = ud->dev; in udma_setup_rx_flush()
5158 rx_flush->buffer_size = SZ_1K; in udma_setup_rx_flush()
5159 rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size, in udma_setup_rx_flush()
5161 if (!rx_flush->buffer_vaddr) in udma_setup_rx_flush()
5162 return -ENOMEM; in udma_setup_rx_flush()
5164 rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr, in udma_setup_rx_flush()
5165 rx_flush->buffer_size, in udma_setup_rx_flush()
5167 if (dma_mapping_error(dev, rx_flush->buffer_paddr)) in udma_setup_rx_flush()
5168 return -ENOMEM; in udma_setup_rx_flush()
5171 hwdesc = &rx_flush->hwdescs[0]; in udma_setup_rx_flush()
5173 hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1); in udma_setup_rx_flush()
5174 hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5175 ud->desc_align); in udma_setup_rx_flush()
5177 hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5179 if (!hwdesc->cppi5_desc_vaddr) in udma_setup_rx_flush()
5180 return -ENOMEM; in udma_setup_rx_flush()
5182 hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, in udma_setup_rx_flush()
5183 hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5185 if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) in udma_setup_rx_flush()
5186 return -ENOMEM; in udma_setup_rx_flush()
5189 hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; in udma_setup_rx_flush()
5191 hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size; in udma_setup_rx_flush()
5193 tr_desc = hwdesc->cppi5_desc_vaddr; in udma_setup_rx_flush()
5198 tr_req = hwdesc->tr_req_base; in udma_setup_rx_flush()
5199 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, in udma_setup_rx_flush()
5201 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); in udma_setup_rx_flush()
5203 tr_req->addr = rx_flush->buffer_paddr; in udma_setup_rx_flush()
5204 tr_req->icnt0 = rx_flush->buffer_size; in udma_setup_rx_flush()
5205 tr_req->icnt1 = 1; in udma_setup_rx_flush()
5207 dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, in udma_setup_rx_flush()
5208 hwdesc->cppi5_desc_size, DMA_TO_DEVICE); in udma_setup_rx_flush()
5211 hwdesc = &rx_flush->hwdescs[1]; in udma_setup_rx_flush()
5212 hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + in udma_setup_rx_flush()
5215 ud->desc_align); in udma_setup_rx_flush()
5217 hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5219 if (!hwdesc->cppi5_desc_vaddr) in udma_setup_rx_flush()
5220 return -ENOMEM; in udma_setup_rx_flush()
5222 hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, in udma_setup_rx_flush()
5223 hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5225 if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) in udma_setup_rx_flush()
5226 return -ENOMEM; in udma_setup_rx_flush()
5228 desc = hwdesc->cppi5_desc_vaddr; in udma_setup_rx_flush()
5230 cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); in udma_setup_rx_flush()
5231 cppi5_desc_set_retpolicy(&desc->hdr, 0, 0); in udma_setup_rx_flush()
5234 rx_flush->buffer_paddr, rx_flush->buffer_size, in udma_setup_rx_flush()
5235 rx_flush->buffer_paddr, rx_flush->buffer_size); in udma_setup_rx_flush()
5237 dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, in udma_setup_rx_flush()
5238 hwdesc->cppi5_desc_size, DMA_TO_DEVICE); in udma_setup_rx_flush()
5247 struct udma_chan_config *ucc = &uc->config; in udma_dbg_summary_show_chan()
5249 seq_printf(s, " %-13s| %s", dma_chan_name(chan), in udma_dbg_summary_show_chan()
5250 chan->dbg_client_name ?: "in-use"); in udma_dbg_summary_show_chan()
5251 if (ucc->tr_trigger_type) in udma_dbg_summary_show_chan()
5255 dmaengine_get_direction_text(uc->config.dir)); in udma_dbg_summary_show_chan()
5257 switch (uc->config.dir) { in udma_dbg_summary_show_chan()
5259 if (uc->ud->match_data->type == DMA_TYPE_BCDMA) { in udma_dbg_summary_show_chan()
5260 seq_printf(s, "bchan%d)\n", uc->bchan->id); in udma_dbg_summary_show_chan()
5264 seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id, in udma_dbg_summary_show_chan()
5265 ucc->src_thread, ucc->dst_thread); in udma_dbg_summary_show_chan()
5268 seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id, in udma_dbg_summary_show_chan()
5269 ucc->src_thread, ucc->dst_thread); in udma_dbg_summary_show_chan()
5270 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) in udma_dbg_summary_show_chan()
5271 seq_printf(s, "rflow%d, ", uc->rflow->id); in udma_dbg_summary_show_chan()
5274 seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id, in udma_dbg_summary_show_chan()
5275 ucc->src_thread, ucc->dst_thread); in udma_dbg_summary_show_chan()
5276 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) in udma_dbg_summary_show_chan()
5277 seq_printf(s, "tflow%d, ", uc->tchan->tflow_id); in udma_dbg_summary_show_chan()
5284 if (ucc->ep_type == PSIL_EP_NATIVE) { in udma_dbg_summary_show_chan()
5285 seq_printf(s, "PSI-L Native"); in udma_dbg_summary_show_chan()
5286 if (ucc->metadata_size) { in udma_dbg_summary_show_chan()
5287 seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : ""); in udma_dbg_summary_show_chan()
5288 if (ucc->psd_size) in udma_dbg_summary_show_chan()
5289 seq_printf(s, " PSDsize:%u", ucc->psd_size); in udma_dbg_summary_show_chan()
5294 if (ucc->enable_acc32 || ucc->enable_burst) in udma_dbg_summary_show_chan()
5296 ucc->enable_acc32 ? " ACC32" : "", in udma_dbg_summary_show_chan()
5297 ucc->enable_burst ? " BURST" : ""); in udma_dbg_summary_show_chan()
5300 seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode"); in udma_dbg_summary_show_chan()
5308 list_for_each_entry(chan, &dma_dev->channels, device_node) { in udma_dbg_summary_show()
5309 if (chan->client_count) in udma_dbg_summary_show()
5317 const struct udma_match_data *match_data = ud->match_data; in udma_get_copy_align()
5318 u8 tpl; in udma_get_copy_align() local
5320 if (!match_data->enable_memcpy_support) in udma_get_copy_align()
5323 /* Get the highest TPL level the device supports for memcpy */ in udma_get_copy_align()
5324 if (ud->bchan_cnt) in udma_get_copy_align()
5325 tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0); in udma_get_copy_align()
5326 else if (ud->tchan_cnt) in udma_get_copy_align()
5327 tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0); in udma_get_copy_align()
5331 switch (match_data->burst_size[tpl]) { in udma_get_copy_align()
5351 struct device_node *navss_node = pdev->dev.parent->of_node; in udma_probe()
5353 struct device *dev = &pdev->dev; in udma_probe()
5365 return -ENOMEM; in udma_probe()
5367 match = of_match_node(udma_of_match, dev->of_node); in udma_probe()
5370 return -ENODEV; in udma_probe()
5372 ud->match_data = match->data; in udma_probe()
5374 ud->soc_data = ud->match_data->soc_data; in udma_probe()
5375 if (!ud->soc_data) { in udma_probe()
5379 return -ENODEV; in udma_probe()
5381 ud->soc_data = soc->data; in udma_probe()
5388 ud->tisci_rm.tisci = ti_sci_get_by_phandle(dev->of_node, "ti,sci"); in udma_probe()
5389 if (IS_ERR(ud->tisci_rm.tisci)) in udma_probe()
5390 return PTR_ERR(ud->tisci_rm.tisci); in udma_probe()
5392 ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", in udma_probe()
5393 &ud->tisci_rm.tisci_dev_id); in udma_probe()
5395 dev_err(dev, "ti,sci-dev-id read failure %d\n", ret); in udma_probe()
5398 pdev->id = ud->tisci_rm.tisci_dev_id; in udma_probe()
5400 ret = of_property_read_u32(navss_node, "ti,sci-dev-id", in udma_probe()
5401 &ud->tisci_rm.tisci_navss_dev_id); in udma_probe()
5403 dev_err(dev, "NAVSS ti,sci-dev-id read failure %d\n", ret); in udma_probe()
5407 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_probe()
5408 ret = of_property_read_u32(dev->of_node, "ti,udma-atype", in udma_probe()
5409 &ud->atype); in udma_probe()
5410 if (!ret && ud->atype > 2) { in udma_probe()
5411 dev_err(dev, "Invalid atype: %u\n", ud->atype); in udma_probe()
5412 return -EINVAL; in udma_probe()
5415 ret = of_property_read_u32(dev->of_node, "ti,asel", in udma_probe()
5416 &ud->asel); in udma_probe()
5417 if (!ret && ud->asel > 15) { in udma_probe()
5418 dev_err(dev, "Invalid asel: %u\n", ud->asel); in udma_probe()
5419 return -EINVAL; in udma_probe()
5423 ud->tisci_rm.tisci_udmap_ops = &ud->tisci_rm.tisci->ops.rm_udmap_ops; in udma_probe()
5424 ud->tisci_rm.tisci_psil_ops = &ud->tisci_rm.tisci->ops.rm_psil_ops; in udma_probe()
5426 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_probe()
5427 ud->ringacc = of_k3_ringacc_get_by_phandle(dev->of_node, "ti,ringacc"); in udma_probe()
5431 ring_init_data.tisci = ud->tisci_rm.tisci; in udma_probe()
5432 ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id; in udma_probe()
5433 if (ud->match_data->type == DMA_TYPE_BCDMA) { in udma_probe()
5434 ring_init_data.num_rings = ud->bchan_cnt + in udma_probe()
5435 ud->tchan_cnt + in udma_probe()
5436 ud->rchan_cnt; in udma_probe()
5438 ring_init_data.num_rings = ud->rflow_cnt + in udma_probe()
5439 ud->tflow_cnt; in udma_probe()
5442 ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data); in udma_probe()
5445 if (IS_ERR(ud->ringacc)) in udma_probe()
5446 return PTR_ERR(ud->ringacc); in udma_probe()
5448 dev->msi.domain = of_msi_get_domain(dev, dev->of_node, in udma_probe()
5450 if (!dev->msi.domain) { in udma_probe()
5451 return -EPROBE_DEFER; in udma_probe()
5454 dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask); in udma_probe()
5456 if (ud->match_data->type != DMA_TYPE_PKTDMA) { in udma_probe()
5457 dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); in udma_probe()
5458 ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic; in udma_probe()
5461 ud->ddev.device_config = udma_slave_config; in udma_probe()
5462 ud->ddev.device_prep_slave_sg = udma_prep_slave_sg; in udma_probe()
5463 ud->ddev.device_issue_pending = udma_issue_pending; in udma_probe()
5464 ud->ddev.device_tx_status = udma_tx_status; in udma_probe()
5465 ud->ddev.device_pause = udma_pause; in udma_probe()
5466 ud->ddev.device_resume = udma_resume; in udma_probe()
5467 ud->ddev.device_terminate_all = udma_terminate_all; in udma_probe()
5468 ud->ddev.device_synchronize = udma_synchronize; in udma_probe()
5470 ud->ddev.dbg_summary_show = udma_dbg_summary_show; in udma_probe()
5473 switch (ud->match_data->type) { in udma_probe()
5475 ud->ddev.device_alloc_chan_resources = in udma_probe()
5479 ud->ddev.device_alloc_chan_resources = in udma_probe()
5481 ud->ddev.device_router_config = bcdma_router_config; in udma_probe()
5484 ud->ddev.device_alloc_chan_resources = in udma_probe()
5488 return -EINVAL; in udma_probe()
5490 ud->ddev.device_free_chan_resources = udma_free_chan_resources; in udma_probe()
5492 ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS; in udma_probe()
5493 ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS; in udma_probe()
5494 ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in udma_probe()
5495 ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in udma_probe()
5496 ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT | in udma_probe()
5498 if (ud->match_data->enable_memcpy_support && in udma_probe()
5499 !(ud->match_data->type == DMA_TYPE_BCDMA && ud->bchan_cnt == 0)) { in udma_probe()
5500 dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask); in udma_probe()
5501 ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy; in udma_probe()
5502 ud->ddev.directions |= BIT(DMA_MEM_TO_MEM); in udma_probe()
5505 ud->ddev.dev = dev; in udma_probe()
5506 ud->dev = dev; in udma_probe()
5507 ud->psil_base = ud->match_data->psil_base; in udma_probe()
5509 INIT_LIST_HEAD(&ud->ddev.channels); in udma_probe()
5510 INIT_LIST_HEAD(&ud->desc_to_purge); in udma_probe()
5516 spin_lock_init(&ud->lock); in udma_probe()
5517 INIT_WORK(&ud->purge_work, udma_purge_desc_work); in udma_probe()
5519 ud->desc_align = 64; in udma_probe()
5520 if (ud->desc_align < dma_get_cache_alignment()) in udma_probe()
5521 ud->desc_align = dma_get_cache_alignment(); in udma_probe()
5527 for (i = 0; i < ud->bchan_cnt; i++) { in udma_probe()
5528 struct udma_bchan *bchan = &ud->bchans[i]; in udma_probe()
5530 bchan->id = i; in udma_probe()
5531 bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000; in udma_probe()
5534 for (i = 0; i < ud->tchan_cnt; i++) { in udma_probe()
5535 struct udma_tchan *tchan = &ud->tchans[i]; in udma_probe()
5537 tchan->id = i; in udma_probe()
5538 tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + i * 0x1000; in udma_probe()
5541 for (i = 0; i < ud->rchan_cnt; i++) { in udma_probe()
5542 struct udma_rchan *rchan = &ud->rchans[i]; in udma_probe()
5544 rchan->id = i; in udma_probe()
5545 rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + i * 0x1000; in udma_probe()
5548 for (i = 0; i < ud->rflow_cnt; i++) { in udma_probe()
5549 struct udma_rflow *rflow = &ud->rflows[i]; in udma_probe()
5551 rflow->id = i; in udma_probe()
5555 struct udma_chan *uc = &ud->channels[i]; in udma_probe()
5557 uc->ud = ud; in udma_probe()
5558 uc->vc.desc_free = udma_desc_free; in udma_probe()
5559 uc->id = i; in udma_probe()
5560 uc->bchan = NULL; in udma_probe()
5561 uc->tchan = NULL; in udma_probe()
5562 uc->rchan = NULL; in udma_probe()
5563 uc->config.remote_thread_id = -1; in udma_probe()
5564 uc->config.mapped_channel_id = -1; in udma_probe()
5565 uc->config.default_flow_id = -1; in udma_probe()
5566 uc->config.dir = DMA_MEM_TO_MEM; in udma_probe()
5567 uc->name = devm_kasprintf(dev, GFP_KERNEL, "%s chan%d", in udma_probe()
5570 vchan_init(&uc->vc, &ud->ddev); in udma_probe()
5572 tasklet_setup(&uc->vc.task, udma_vchan_complete); in udma_probe()
5573 init_completion(&uc->teardown_completed); in udma_probe()
5574 INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); in udma_probe()
5578 ud->ddev.copy_align = udma_get_copy_align(ud); in udma_probe()
5580 ret = dma_async_device_register(&ud->ddev); in udma_probe()
5588 ret = of_dma_controller_register(dev->of_node, udma_of_xlate, ud); in udma_probe()
5591 dma_async_device_unregister(&ud->ddev); in udma_probe()
5600 struct dma_device *dma_dev = &ud->ddev; in udma_pm_suspend()
5604 list_for_each_entry(chan, &dma_dev->channels, device_node) { in udma_pm_suspend()
5605 if (chan->client_count) { in udma_pm_suspend()
5608 memcpy(&uc->backup_config, &uc->config, in udma_pm_suspend()
5612 ud->ddev.device_free_chan_resources(chan); in udma_pm_suspend()
5622 struct dma_device *dma_dev = &ud->ddev; in udma_pm_resume()
5627 list_for_each_entry(chan, &dma_dev->channels, device_node) { in udma_pm_resume()
5628 if (chan->client_count) { in udma_pm_resume()
5631 memcpy(&uc->config, &uc->backup_config, in udma_pm_resume()
5635 ret = ud->ddev.device_alloc_chan_resources(chan); in udma_pm_resume()
5650 .name = "ti-udma",
5659 MODULE_DESCRIPTION("Texas Instruments UDMA support");
5663 #include "k3-udma-private.c"