163 	const struct tegra_adma_chip_data *cdata;  member
171 	writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);  in tdma_write()
176 	return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);  in tdma_read()
226 	tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1);  in tegra_adma_init()
234 				 tdma->cdata->global_reg_offset +  in tegra_adma_init()
255 	if (sreq_index > tdma->cdata->ch_req_max) {  in tegra_adma_request_alloc()
561 	const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;  in tegra_adma_set_xfer_params()  local
574 						      cdata->ch_req_mask,  in tegra_adma_set_xfer_params()
575 						      cdata->ch_req_tx_shift);  in tegra_adma_set_xfer_params()
585 						      cdata->ch_req_mask,  in tegra_adma_set_xfer_params()
586 						      cdata->ch_req_rx_shift);  in tegra_adma_set_xfer_params()
598 	ch_regs->config |= cdata->adma_get_burst_config(burst_size);  in tegra_adma_set_xfer_params()
600 	if (cdata->has_outstanding_reqs)  in tegra_adma_set_xfer_params()
614 	if (tdc->sreq_index > cdata->sreq_index_offset)  in tegra_adma_set_xfer_params()
616 			ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask,  in tegra_adma_set_xfer_params()
620 			ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask,  in tegra_adma_set_xfer_params()
847 	const struct tegra_adma_chip_data *cdata;  in tegra_adma_probe()  local
851 	cdata = of_device_get_match_data(&pdev->dev);  in tegra_adma_probe()
852 	if (!cdata) {  in tegra_adma_probe()
858 			    struct_size(tdma, channels, cdata->nr_channels),  in tegra_adma_probe()
864 	tdma->cdata = cdata;  in tegra_adma_probe()
865 	tdma->nr_channels = cdata->nr_channels;  in tegra_adma_probe()
903 		tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset  in tegra_adma_probe()
904 				 + (cdata->ch_reg_size * i);  in tegra_adma_probe()