Lines Matching +full:tegra210 +full:- +full:admaif
1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADMA driver for Nvidia's Tegra210 ADMA controller.
18 #include "virt-dma.h"
68 * struct tegra_adma_chip_data - Tegra chip specific data
102 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
115 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
126 * struct tegra_adma_chan - Tegra ADMA channel information
148 * struct tegra_adma - Tegra ADMA controller information
171 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_write()
176 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_read()
181 writel(val, tdc->chan_addr + reg); in tdma_ch_write()
186 return readl(tdc->chan_addr + reg); in tdma_ch_read()
202 return tdc->tdma->dev; in tdc2dev()
215 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); in tegra_adma_slave_config()
226 tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); in tegra_adma_init()
233 tdma->base_addr + in tegra_adma_init()
234 tdma->cdata->global_reg_offset + in tegra_adma_init()
249 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_alloc()
250 unsigned int sreq_index = tdc->sreq_index; in tegra_adma_request_alloc()
252 if (tdc->sreq_reserved) in tegra_adma_request_alloc()
253 return tdc->sreq_dir == direction ? 0 : -EINVAL; in tegra_adma_request_alloc()
255 if (sreq_index > tdma->cdata->ch_req_max) { in tegra_adma_request_alloc()
256 dev_err(tdma->dev, "invalid DMA request\n"); in tegra_adma_request_alloc()
257 return -EINVAL; in tegra_adma_request_alloc()
262 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { in tegra_adma_request_alloc()
263 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
264 return -EINVAL; in tegra_adma_request_alloc()
269 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { in tegra_adma_request_alloc()
270 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
271 return -EINVAL; in tegra_adma_request_alloc()
276 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_alloc()
277 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_alloc()
278 return -EINVAL; in tegra_adma_request_alloc()
281 tdc->sreq_dir = direction; in tegra_adma_request_alloc()
282 tdc->sreq_reserved = true; in tegra_adma_request_alloc()
289 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_free()
291 if (!tdc->sreq_reserved) in tegra_adma_request_free()
294 switch (tdc->sreq_dir) { in tegra_adma_request_free()
296 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); in tegra_adma_request_free()
300 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); in tegra_adma_request_free()
304 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_free()
305 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_free()
309 tdc->sreq_reserved = false; in tegra_adma_request_free()
339 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, in tegra_adma_stop()
346 kfree(tdc->desc); in tegra_adma_stop()
347 tdc->desc = NULL; in tegra_adma_stop()
352 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); in tegra_adma_start()
359 list_del(&vd->node); in tegra_adma_start()
361 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_start()
368 ch_regs = &desc->ch_regs; in tegra_adma_start()
370 tdc->tx_buf_pos = 0; in tegra_adma_start()
371 tdc->tx_buf_count = 0; in tegra_adma_start()
372 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); in tegra_adma_start()
373 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_start()
374 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); in tegra_adma_start()
375 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); in tegra_adma_start()
376 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); in tegra_adma_start()
377 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); in tegra_adma_start()
382 tdc->desc = desc; in tegra_adma_start()
387 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_get_residue()
395 if (pos < tdc->tx_buf_pos) in tegra_adma_get_residue()
396 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); in tegra_adma_get_residue()
398 tdc->tx_buf_count += pos - tdc->tx_buf_pos; in tegra_adma_get_residue()
400 periods_remaining = tdc->tx_buf_count % desc->num_periods; in tegra_adma_get_residue()
401 tdc->tx_buf_pos = pos; in tegra_adma_get_residue()
403 return desc->buf_len - (periods_remaining * desc->period_len); in tegra_adma_get_residue()
411 spin_lock(&tdc->vc.lock); in tegra_adma_isr()
414 if (status == 0 || !tdc->desc) { in tegra_adma_isr()
415 spin_unlock(&tdc->vc.lock); in tegra_adma_isr()
419 vchan_cyclic_callback(&tdc->desc->vd); in tegra_adma_isr()
421 spin_unlock(&tdc->vc.lock); in tegra_adma_isr()
431 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
433 if (vchan_issue_pending(&tdc->vc)) { in tegra_adma_issue_pending()
434 if (!tdc->desc) in tegra_adma_issue_pending()
438 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
454 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_pause()
455 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_pause()
458 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_pause()
459 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_pause()
460 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_pause()
462 while (dcnt-- && !tegra_adma_is_paused(tdc)) in tegra_adma_pause()
467 return -EBUSY; in tegra_adma_pause()
476 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_resume()
477 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_resume()
479 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_resume()
480 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_resume()
481 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_resume()
492 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
494 if (tdc->desc) in tegra_adma_terminate_all()
498 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_adma_terminate_all()
499 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
500 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_adma_terminate_all()
520 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_tx_status()
522 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_adma_tx_status()
524 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_tx_status()
525 residual = desc->ch_regs.tc; in tegra_adma_tx_status()
526 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { in tegra_adma_tx_status()
532 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_tx_status()
552 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; in tegra186_adma_get_burst_config()
560 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_set_xfer_params()
561 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; in tegra_adma_set_xfer_params()
564 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) in tegra_adma_set_xfer_params()
565 return -EINVAL; in tegra_adma_set_xfer_params()
571 burst_size = tdc->sconfig.dst_maxburst; in tegra_adma_set_xfer_params()
572 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
573 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
574 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
575 cdata->ch_req_tx_shift); in tegra_adma_set_xfer_params()
576 ch_regs->src_addr = buf_addr; in tegra_adma_set_xfer_params()
582 burst_size = tdc->sconfig.src_maxburst; in tegra_adma_set_xfer_params()
583 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
584 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
585 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
586 cdata->ch_req_rx_shift); in tegra_adma_set_xfer_params()
587 ch_regs->trg_addr = buf_addr; in tegra_adma_set_xfer_params()
592 return -EINVAL; in tegra_adma_set_xfer_params()
595 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) | in tegra_adma_set_xfer_params()
598 ch_regs->config |= cdata->adma_get_burst_config(burst_size); in tegra_adma_set_xfer_params()
599 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); in tegra_adma_set_xfer_params()
600 if (cdata->has_outstanding_reqs) in tegra_adma_set_xfer_params()
601 ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8); in tegra_adma_set_xfer_params()
604 * 'sreq_index' represents the current ADMAIF channel number and as per in tegra_adma_set_xfer_params()
608 * ADMA FIFO size is set as per below (based on default ADMAIF channel in tegra_adma_set_xfer_params()
614 if (tdc->sreq_index > cdata->sreq_index_offset) in tegra_adma_set_xfer_params()
615 ch_regs->fifo_ctrl = in tegra_adma_set_xfer_params()
616 ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask, in tegra_adma_set_xfer_params()
619 ch_regs->fifo_ctrl = in tegra_adma_set_xfer_params()
620 ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask, in tegra_adma_set_xfer_params()
623 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; in tegra_adma_set_xfer_params()
655 desc->buf_len = buf_len; in tegra_adma_prep_dma_cyclic()
656 desc->period_len = period_len; in tegra_adma_prep_dma_cyclic()
657 desc->num_periods = buf_len / period_len; in tegra_adma_prep_dma_cyclic()
664 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); in tegra_adma_prep_dma_cyclic()
672 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); in tegra_adma_alloc_chan_resources()
681 free_irq(tdc->irq, tdc); in tegra_adma_alloc_chan_resources()
685 dma_cookie_init(&tdc->vc.chan); in tegra_adma_alloc_chan_resources()
695 vchan_free_chan_resources(&tdc->vc); in tegra_adma_free_chan_resources()
696 tasklet_kill(&tdc->vc.task); in tegra_adma_free_chan_resources()
697 free_irq(tdc->irq, tdc); in tegra_adma_free_chan_resources()
700 tdc->sreq_index = 0; in tegra_adma_free_chan_resources()
701 tdc->sreq_dir = DMA_TRANS_NONE; in tegra_adma_free_chan_resources()
707 struct tegra_adma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
712 if (dma_spec->args_count != 1) in tegra_dma_of_xlate()
715 sreq_index = dma_spec->args[0]; in tegra_dma_of_xlate()
718 dev_err(tdma->dev, "DMA request must not be 0\n"); in tegra_dma_of_xlate()
722 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
727 tdc->sreq_index = sreq_index; in tegra_dma_of_xlate()
739 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); in tegra_adma_runtime_suspend()
740 if (!tdma->global_cmd) in tegra_adma_runtime_suspend()
743 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_suspend()
744 tdc = &tdma->channels[i]; in tegra_adma_runtime_suspend()
746 if (!tdc->tdma) in tegra_adma_runtime_suspend()
749 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_suspend()
750 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); in tegra_adma_runtime_suspend()
752 if (!ch_reg->cmd) in tegra_adma_runtime_suspend()
754 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC); in tegra_adma_runtime_suspend()
755 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); in tegra_adma_runtime_suspend()
756 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); in tegra_adma_runtime_suspend()
757 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_runtime_suspend()
758 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); in tegra_adma_runtime_suspend()
759 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); in tegra_adma_runtime_suspend()
763 clk_disable_unprepare(tdma->ahub_clk); in tegra_adma_runtime_suspend()
775 ret = clk_prepare_enable(tdma->ahub_clk); in tegra_adma_runtime_resume()
780 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); in tegra_adma_runtime_resume()
782 if (!tdma->global_cmd) in tegra_adma_runtime_resume()
785 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_resume()
786 tdc = &tdma->channels[i]; in tegra_adma_runtime_resume()
788 if (!tdc->tdma) in tegra_adma_runtime_resume()
790 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_resume()
792 if (!ch_reg->cmd) in tegra_adma_runtime_resume()
794 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); in tegra_adma_runtime_resume()
795 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); in tegra_adma_runtime_resume()
796 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); in tegra_adma_runtime_resume()
797 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); in tegra_adma_runtime_resume()
798 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); in tegra_adma_runtime_resume()
799 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); in tegra_adma_runtime_resume()
800 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); in tegra_adma_runtime_resume()
839 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
840 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
851 cdata = of_device_get_match_data(&pdev->dev); in tegra_adma_probe()
853 dev_err(&pdev->dev, "device match data not found\n"); in tegra_adma_probe()
854 return -ENODEV; in tegra_adma_probe()
857 tdma = devm_kzalloc(&pdev->dev, in tegra_adma_probe()
858 struct_size(tdma, channels, cdata->nr_channels), in tegra_adma_probe()
861 return -ENOMEM; in tegra_adma_probe()
863 tdma->dev = &pdev->dev; in tegra_adma_probe()
864 tdma->cdata = cdata; in tegra_adma_probe()
865 tdma->nr_channels = cdata->nr_channels; in tegra_adma_probe()
868 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_adma_probe()
869 if (IS_ERR(tdma->base_addr)) in tegra_adma_probe()
870 return PTR_ERR(tdma->base_addr); in tegra_adma_probe()
872 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); in tegra_adma_probe()
873 if (IS_ERR(tdma->ahub_clk)) { in tegra_adma_probe()
874 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); in tegra_adma_probe()
875 return PTR_ERR(tdma->ahub_clk); in tegra_adma_probe()
878 tdma->dma_chan_mask = devm_kzalloc(&pdev->dev, in tegra_adma_probe()
879 BITS_TO_LONGS(tdma->nr_channels) * sizeof(unsigned long), in tegra_adma_probe()
881 if (!tdma->dma_chan_mask) in tegra_adma_probe()
882 return -ENOMEM; in tegra_adma_probe()
885 bitmap_fill(tdma->dma_chan_mask, tdma->nr_channels); in tegra_adma_probe()
887 ret = of_property_read_u32_array(pdev->dev.of_node, "dma-channel-mask", in tegra_adma_probe()
888 (u32 *)tdma->dma_chan_mask, in tegra_adma_probe()
889 BITS_TO_U32(tdma->nr_channels)); in tegra_adma_probe()
890 if (ret < 0 && (ret != -EINVAL)) { in tegra_adma_probe()
891 dev_err(&pdev->dev, "dma-channel-mask is not complete.\n"); in tegra_adma_probe()
895 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_adma_probe()
896 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_probe()
897 struct tegra_adma_chan *tdc = &tdma->channels[i]; in tegra_adma_probe()
900 if (!test_bit(i, tdma->dma_chan_mask)) in tegra_adma_probe()
903 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset in tegra_adma_probe()
904 + (cdata->ch_reg_size * i); in tegra_adma_probe()
906 tdc->irq = of_irq_get(pdev->dev.of_node, i); in tegra_adma_probe()
907 if (tdc->irq <= 0) { in tegra_adma_probe()
908 ret = tdc->irq ?: -ENXIO; in tegra_adma_probe()
912 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_adma_probe()
913 tdc->vc.desc_free = tegra_adma_desc_free; in tegra_adma_probe()
914 tdc->tdma = tdma; in tegra_adma_probe()
917 pm_runtime_enable(&pdev->dev); in tegra_adma_probe()
919 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_adma_probe()
927 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
928 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
929 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_adma_probe()
931 tdma->dma_dev.dev = &pdev->dev; in tegra_adma_probe()
932 tdma->dma_dev.device_alloc_chan_resources = in tegra_adma_probe()
934 tdma->dma_dev.device_free_chan_resources = in tegra_adma_probe()
936 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; in tegra_adma_probe()
937 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; in tegra_adma_probe()
938 tdma->dma_dev.device_config = tegra_adma_slave_config; in tegra_adma_probe()
939 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; in tegra_adma_probe()
940 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; in tegra_adma_probe()
941 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
942 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
943 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_adma_probe()
944 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in tegra_adma_probe()
945 tdma->dma_dev.device_pause = tegra_adma_pause; in tegra_adma_probe()
946 tdma->dma_dev.device_resume = tegra_adma_resume; in tegra_adma_probe()
948 ret = dma_async_device_register(&tdma->dma_dev); in tegra_adma_probe()
950 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); in tegra_adma_probe()
954 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_adma_probe()
957 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); in tegra_adma_probe()
961 pm_runtime_put(&pdev->dev); in tegra_adma_probe()
963 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", in tegra_adma_probe()
964 tdma->nr_channels); in tegra_adma_probe()
969 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_probe()
971 pm_runtime_put_sync(&pdev->dev); in tegra_adma_probe()
973 pm_runtime_disable(&pdev->dev); in tegra_adma_probe()
975 while (--i >= 0) in tegra_adma_probe()
976 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_probe()
986 of_dma_controller_free(pdev->dev.of_node); in tegra_adma_remove()
987 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_remove()
989 for (i = 0; i < tdma->nr_channels; ++i) { in tegra_adma_remove()
990 if (tdma->channels[i].irq) in tegra_adma_remove()
991 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_remove()
994 pm_runtime_disable(&pdev->dev); in tegra_adma_remove()
1006 .name = "tegra-adma",
1016 MODULE_ALIAS("platform:tegra210-adma");