184 	int (*terminate)(struct tegra_dma_channel *tdc);
223 	struct tegra_dma_channel *tdc;  member
260 static inline void tdc_write(struct tegra_dma_channel *tdc,  in tdc_write()  argument
263 	writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);  in tdc_write()
266 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)  in tdc_read()  argument
268 	return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);  in tdc_read()
281 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)  in tdc2dev()  argument
283 	return tdc->vc.chan.device->dev;  in tdc2dev()
286 static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)  in tegra_dma_dump_chan_regs()  argument
288 	dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",  in tegra_dma_dump_chan_regs()
289 		tdc->id, tdc->name);  in tegra_dma_dump_chan_regs()
290 	dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",  in tegra_dma_dump_chan_regs()
291 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),  in tegra_dma_dump_chan_regs()
292 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),  in tegra_dma_dump_chan_regs()
293 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),  in tegra_dma_dump_chan_regs()
294 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),  in tegra_dma_dump_chan_regs()
295 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)  in tegra_dma_dump_chan_regs()
297 	dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",  in tegra_dma_dump_chan_regs()
298 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),  in tegra_dma_dump_chan_regs()
299 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),  in tegra_dma_dump_chan_regs()
300 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),  in tegra_dma_dump_chan_regs()
301 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),  in tegra_dma_dump_chan_regs()
302 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)  in tegra_dma_dump_chan_regs()
304 	dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",  in tegra_dma_dump_chan_regs()
305 		tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));  in tegra_dma_dump_chan_regs()
308 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,  in tegra_dma_sid_reserve()  argument
311 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_sid_reserve()
312 	int sid = tdc->slave_id;  in tegra_dma_sid_reserve()
334 	tdc->sid_dir = direction;  in tegra_dma_sid_reserve()
339 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)  in tegra_dma_sid_free()  argument
341 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_sid_free()
342 	int sid = tdc->slave_id;  in tegra_dma_sid_free()
344 	switch (tdc->sid_dir) {  in tegra_dma_sid_free()
355 	tdc->sid_dir = DMA_TRANS_NONE;  in tegra_dma_sid_free()
366 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_slave_config()  local
368 	memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));  in tegra_dma_slave_config()
369 	tdc->config_init = true;  in tegra_dma_slave_config()
374 static int tegra_dma_pause(struct tegra_dma_channel *tdc)  in tegra_dma_pause()  argument
379 	val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);  in tegra_dma_pause()
381 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);  in tegra_dma_pause()
384 	ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +  in tegra_dma_pause()
385 			tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,  in tegra_dma_pause()
392 		dev_err(tdc2dev(tdc), "DMA pause timed out\n");  in tegra_dma_pause()
393 		tegra_dma_dump_chan_regs(tdc);  in tegra_dma_pause()
401 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_device_pause()  local
405 	if (!tdc->tdma->chip_data->hw_support_pause)  in tegra_dma_device_pause()
408 	spin_lock_irqsave(&tdc->vc.lock, flags);  in tegra_dma_device_pause()
409 	ret = tegra_dma_pause(tdc);  in tegra_dma_device_pause()
410 	spin_unlock_irqrestore(&tdc->vc.lock, flags);  in tegra_dma_device_pause()
415 static void tegra_dma_resume(struct tegra_dma_channel *tdc)  in tegra_dma_resume()  argument
419 	val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);  in tegra_dma_resume()
421 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);  in tegra_dma_resume()
426 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_device_resume()  local
429 	if (!tdc->tdma->chip_data->hw_support_pause)  in tegra_dma_device_resume()
432 	spin_lock_irqsave(&tdc->vc.lock, flags);  in tegra_dma_device_resume()
433 	tegra_dma_resume(tdc);  in tegra_dma_device_resume()
434 	spin_unlock_irqrestore(&tdc->vc.lock, flags);  in tegra_dma_device_resume()
439 static inline int tegra_dma_pause_noerr(struct tegra_dma_channel *tdc)  in tegra_dma_pause_noerr()  argument
446 	tegra_dma_pause(tdc);  in tegra_dma_pause_noerr()
450 static void tegra_dma_disable(struct tegra_dma_channel *tdc)  in tegra_dma_disable()  argument
454 	csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);  in tegra_dma_disable()
461 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);  in tegra_dma_disable()
464 	status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);  in tegra_dma_disable()
466 		dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);  in tegra_dma_disable()
467 		tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);  in tegra_dma_disable()
471 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)  in tegra_dma_configure_next_sg()  argument
473 	struct tegra_dma_desc *dma_desc = tdc->dma_desc;  in tegra_dma_configure_next_sg()
485 	ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +  in tegra_dma_configure_next_sg()
486 			tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,  in tegra_dma_configure_next_sg()
495 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_configure_next_sg()
496 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);  in tegra_dma_configure_next_sg()
497 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);  in tegra_dma_configure_next_sg()
498 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);  in tegra_dma_configure_next_sg()
501 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,  in tegra_dma_configure_next_sg()
505 static void tegra_dma_start(struct tegra_dma_channel *tdc)  in tegra_dma_start()  argument
507 	struct tegra_dma_desc *dma_desc = tdc->dma_desc;  in tegra_dma_start()
512 		vdesc = vchan_next_desc(&tdc->vc);  in tegra_dma_start()
518 		dma_desc->tdc = tdc;  in tegra_dma_start()
519 		tdc->dma_desc = dma_desc;  in tegra_dma_start()
521 		tegra_dma_resume(tdc);  in tegra_dma_start()
526 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_start()
527 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);  in tegra_dma_start()
528 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);  in tegra_dma_start()
529 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);  in tegra_dma_start()
530 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);  in tegra_dma_start()
531 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);  in tegra_dma_start()
532 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);  in tegra_dma_start()
533 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);  in tegra_dma_start()
534 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);  in tegra_dma_start()
537 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,  in tegra_dma_start()
541 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)  in tegra_dma_xfer_complete()  argument
543 	vchan_cookie_complete(&tdc->dma_desc->vd);  in tegra_dma_xfer_complete()
545 	tegra_dma_sid_free(tdc);  in tegra_dma_xfer_complete()
546 	tdc->dma_desc = NULL;  in tegra_dma_xfer_complete()
549 static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,  in tegra_dma_chan_decode_error()  argument
554 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
555 			"GPCDMA CH%d bm fifo full\n", tdc->id);  in tegra_dma_chan_decode_error()
559 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
560 			"GPCDMA CH%d peripheral fifo full\n", tdc->id);  in tegra_dma_chan_decode_error()
564 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
565 			"GPCDMA CH%d illegal peripheral id\n", tdc->id);  in tegra_dma_chan_decode_error()
569 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
570 			"GPCDMA CH%d illegal stream id\n", tdc->id);  in tegra_dma_chan_decode_error()
574 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
575 			"GPCDMA CH%d mc slave error\n", tdc->id);  in tegra_dma_chan_decode_error()
579 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
580 			"GPCDMA CH%d mmio slave error\n", tdc->id);  in tegra_dma_chan_decode_error()
584 		dev_err(tdc->tdma->dev,  in tegra_dma_chan_decode_error()
585 			"GPCDMA CH%d security violation %x\n", tdc->id,  in tegra_dma_chan_decode_error()
592 	struct tegra_dma_channel *tdc = dev_id;  in tegra_dma_isr()  local
593 	struct tegra_dma_desc *dma_desc = tdc->dma_desc;  in tegra_dma_isr()
598 	status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);  in tegra_dma_isr()
600 		tegra_dma_chan_decode_error(tdc, status);  in tegra_dma_isr()
601 		tegra_dma_dump_chan_regs(tdc);  in tegra_dma_isr()
602 		tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);  in tegra_dma_isr()
605 	spin_lock(&tdc->vc.lock);  in tegra_dma_isr()
606 	status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);  in tegra_dma_isr()
610 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,  in tegra_dma_isr()
621 		tegra_dma_configure_next_sg(tdc);  in tegra_dma_isr()
625 			tegra_dma_xfer_complete(tdc);  in tegra_dma_isr()
627 			tegra_dma_start(tdc);  in tegra_dma_isr()
631 	spin_unlock(&tdc->vc.lock);  in tegra_dma_isr()
637 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_issue_pending()  local
640 	if (tdc->dma_desc)  in tegra_dma_issue_pending()
643 	spin_lock_irqsave(&tdc->vc.lock, flags);  in tegra_dma_issue_pending()
644 	if (vchan_issue_pending(&tdc->vc))  in tegra_dma_issue_pending()
645 		tegra_dma_start(tdc);  in tegra_dma_issue_pending()
654 	if (tdc->dma_desc && tdc->dma_desc->cyclic)  in tegra_dma_issue_pending()
655 		tegra_dma_configure_next_sg(tdc);  in tegra_dma_issue_pending()
657 	spin_unlock_irqrestore(&tdc->vc.lock, flags);  in tegra_dma_issue_pending()
660 static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)  in tegra_dma_stop_client()  argument
670 	csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);  in tegra_dma_stop_client()
673 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);  in tegra_dma_stop_client()
682 	ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +  in tegra_dma_stop_client()
683 				tdc->chan_base_offset +  in tegra_dma_stop_client()
691 		dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");  in tegra_dma_stop_client()
692 		tegra_dma_dump_chan_regs(tdc);  in tegra_dma_stop_client()
700 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_terminate_all()  local
705 	spin_lock_irqsave(&tdc->vc.lock, flags);  in tegra_dma_terminate_all()
707 	if (tdc->dma_desc) {  in tegra_dma_terminate_all()
708 		err = tdc->tdma->chip_data->terminate(tdc);  in tegra_dma_terminate_all()
710 			spin_unlock_irqrestore(&tdc->vc.lock, flags);  in tegra_dma_terminate_all()
714 		vchan_terminate_vdesc(&tdc->dma_desc->vd);  in tegra_dma_terminate_all()
715 		tegra_dma_disable(tdc);  in tegra_dma_terminate_all()
716 		tdc->dma_desc = NULL;  in tegra_dma_terminate_all()
719 	tegra_dma_sid_free(tdc);  in tegra_dma_terminate_all()
720 	vchan_get_all_descriptors(&tdc->vc, &head);  in tegra_dma_terminate_all()
721 	spin_unlock_irqrestore(&tdc->vc.lock, flags);  in tegra_dma_terminate_all()
723 	vchan_dma_desc_free_list(&tdc->vc, &head);  in tegra_dma_terminate_all()
728 static int tegra_dma_get_residual(struct tegra_dma_channel *tdc)  in tegra_dma_get_residual()  argument
730 	struct tegra_dma_desc *dma_desc = tdc->dma_desc;  in tegra_dma_get_residual()
735 	wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);  in tegra_dma_get_residual()
742 	status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);  in tegra_dma_get_residual()
761 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_tx_status()  local
772 	spin_lock_irqsave(&tdc->vc.lock, flags);  in tegra_dma_tx_status()
773 	vd = vchan_find_desc(&tdc->vc, cookie);  in tegra_dma_tx_status()
778 	} else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) {  in tegra_dma_tx_status()
779 		residual =  tegra_dma_get_residual(tdc);  in tegra_dma_tx_status()
782 		dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);  in tegra_dma_tx_status()
784 	spin_unlock_irqrestore(&tdc->vc.lock, flags);  in tegra_dma_tx_status()
789 static inline int get_bus_width(struct tegra_dma_channel *tdc,  in get_bus_width()  argument
800 		dev_err(tdc2dev(tdc), "given slave bus width is not supported\n");  in get_bus_width()
805 static unsigned int get_burst_size(struct tegra_dma_channel *tdc,  in get_burst_size()  argument
828 static int get_transfer_param(struct tegra_dma_channel *tdc,  in get_transfer_param()  argument
838 		*apb_addr = tdc->dma_sconfig.dst_addr;  in get_transfer_param()
839 		*mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);  in get_transfer_param()
840 		*burst_size = tdc->dma_sconfig.dst_maxburst;  in get_transfer_param()
841 		*slave_bw = tdc->dma_sconfig.dst_addr_width;  in get_transfer_param()
845 		*apb_addr = tdc->dma_sconfig.src_addr;  in get_transfer_param()
846 		*mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);  in get_transfer_param()
847 		*burst_size = tdc->dma_sconfig.src_maxburst;  in get_transfer_param()
848 		*slave_bw = tdc->dma_sconfig.src_addr_width;  in get_transfer_param()
852 		dev_err(tdc2dev(tdc), "DMA direction is not supported\n");  in get_transfer_param()
862 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_prep_dma_memset()  local
863 	unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;  in tegra_dma_prep_dma_memset()
869 		dev_err(tdc2dev(tdc),  in tegra_dma_prep_dma_memset()
886 	mc_seq =  tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);  in tegra_dma_prep_dma_memset()
922 	return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);  in tegra_dma_prep_dma_memset()
929 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_prep_dma_memcpy()  local
935 	max_dma_count = tdc->tdma->chip_data->max_dma_count;  in tegra_dma_prep_dma_memcpy()
937 		dev_err(tdc2dev(tdc),  in tegra_dma_prep_dma_memcpy()
954 	mc_seq =  tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);  in tegra_dma_prep_dma_memcpy()
992 	return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);  in tegra_dma_prep_dma_memcpy()
1000 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_prep_slave_sg()  local
1001 	unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;  in tegra_dma_prep_slave_sg()
1011 	if (!tdc->config_init) {  in tegra_dma_prep_slave_sg()
1012 		dev_err(tdc2dev(tdc), "DMA channel is not configured\n");  in tegra_dma_prep_slave_sg()
1016 		dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);  in tegra_dma_prep_slave_sg()
1020 	ret = tegra_dma_sid_reserve(tdc, direction);  in tegra_dma_prep_slave_sg()
1024 	ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,  in tegra_dma_prep_slave_sg()
1032 	csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);  in tegra_dma_prep_slave_sg()
1042 	mc_seq =  tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);  in tegra_dma_prep_slave_sg()
1079 			dev_err(tdc2dev(tdc),  in tegra_dma_prep_slave_sg()
1085 		mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);  in tegra_dma_prep_slave_sg()
1112 	return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);  in tegra_dma_prep_slave_sg()
1123 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_prep_dma_cyclic()  local
1130 		dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");  in tegra_dma_prep_dma_cyclic()
1134 	if (!tdc->config_init) {  in tegra_dma_prep_dma_cyclic()
1135 		dev_err(tdc2dev(tdc), "DMA slave is not configured\n");  in tegra_dma_prep_dma_cyclic()
1139 	ret = tegra_dma_sid_reserve(tdc, direction);  in tegra_dma_prep_dma_cyclic()
1148 		dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");  in tegra_dma_prep_dma_cyclic()
1153 	max_dma_count = tdc->tdma->chip_data->max_dma_count;  in tegra_dma_prep_dma_cyclic()
1155 		dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");  in tegra_dma_prep_dma_cyclic()
1159 	ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,  in tegra_dma_prep_dma_cyclic()
1167 	csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);  in tegra_dma_prep_dma_cyclic()
1179 	mc_seq =  tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);  in tegra_dma_prep_dma_cyclic()
1209 		mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);  in tegra_dma_prep_dma_cyclic()
1236 	return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);  in tegra_dma_prep_dma_cyclic()
1241 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_alloc_chan_resources()  local
1244 	ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);  in tegra_dma_alloc_chan_resources()
1246 		dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name);  in tegra_dma_alloc_chan_resources()
1250 	dma_cookie_init(&tdc->vc.chan);  in tegra_dma_alloc_chan_resources()
1251 	tdc->config_init = false;  in tegra_dma_alloc_chan_resources()
1257 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_chan_synchronize()  local
1259 	synchronize_irq(tdc->irq);  in tegra_dma_chan_synchronize()
1260 	vchan_synchronize(&tdc->vc);  in tegra_dma_chan_synchronize()
1265 	struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);  in tegra_dma_free_chan_resources()  local
1267 	dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);  in tegra_dma_free_chan_resources()
1270 	synchronize_irq(tdc->irq);  in tegra_dma_free_chan_resources()
1272 	tasklet_kill(&tdc->vc.task);  in tegra_dma_free_chan_resources()
1273 	tdc->config_init = false;  in tegra_dma_free_chan_resources()
1274 	tdc->slave_id = -1;  in tegra_dma_free_chan_resources()
1275 	tdc->sid_dir = DMA_TRANS_NONE;  in tegra_dma_free_chan_resources()
1276 	free_irq(tdc->irq, tdc);  in tegra_dma_free_chan_resources()
1278 	vchan_free_chan_resources(&tdc->vc);  in tegra_dma_free_chan_resources()
1285 	struct tegra_dma_channel *tdc;  in tegra_dma_of_xlate()  local
1292 	tdc = to_tegra_dma_chan(chan);  in tegra_dma_of_xlate()
1293 	tdc->slave_id = dma_spec->args[0];  in tegra_dma_of_xlate()
1337 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)  in tegra_dma_program_sid()  argument
1339 	unsigned int reg_val =  tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);  in tegra_dma_program_sid()
1347 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);  in tegra_dma_program_sid()
1400 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_probe()  local
1406 		tdc->irq = platform_get_irq(pdev, i);  in tegra_dma_probe()
1407 		if (tdc->irq < 0)  in tegra_dma_probe()
1408 			return tdc->irq;  in tegra_dma_probe()
1410 		tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET +  in tegra_dma_probe()
1412 		snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);  in tegra_dma_probe()
1413 		tdc->tdma = tdma;  in tegra_dma_probe()
1414 		tdc->id = i;  in tegra_dma_probe()
1415 		tdc->slave_id = -1;  in tegra_dma_probe()
1417 		vchan_init(&tdc->vc, &tdma->dma_dev);  in tegra_dma_probe()
1418 		tdc->vc.desc_free = tegra_dma_desc_free;  in tegra_dma_probe()
1421 		tegra_dma_program_sid(tdc, stream_id);  in tegra_dma_probe()
1422 		tdc->stream_id = stream_id;  in tegra_dma_probe()
1491 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_pm_suspend()  local
1496 		if (tdc->dma_desc) {  in tegra_dma_pm_suspend()
1513 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_pm_resume()  local
1518 		tegra_dma_program_sid(tdc, tdc->stream_id);  in tegra_dma_pm_resume()