208 	struct tegra_dma_channel_regs ch_regs;  member
474 	struct tegra_dma_channel_regs *ch_regs;  in tegra_dma_configure_next_sg()  local
493 	ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;  in tegra_dma_configure_next_sg()
495 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_configure_next_sg()
496 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);  in tegra_dma_configure_next_sg()
497 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);  in tegra_dma_configure_next_sg()
498 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);  in tegra_dma_configure_next_sg()
502 		  ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);  in tegra_dma_configure_next_sg()
508 	struct tegra_dma_channel_regs *ch_regs;  in tegra_dma_start()  local
524 	ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;  in tegra_dma_start()
526 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);  in tegra_dma_start()
528 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);  in tegra_dma_start()
529 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);  in tegra_dma_start()
530 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);  in tegra_dma_start()
531 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);  in tegra_dma_start()
532 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);  in tegra_dma_start()
533 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);  in tegra_dma_start()
534 	tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);  in tegra_dma_start()
538 		  ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);  in tegra_dma_start()
909 	sg_req[0].ch_regs.src_ptr = 0;  in tegra_dma_prep_dma_memset()
910 	sg_req[0].ch_regs.dst_ptr = dest;  in tegra_dma_prep_dma_memset()
911 	sg_req[0].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_memset()
913 	sg_req[0].ch_regs.fixed_pattern = value;  in tegra_dma_prep_dma_memset()
915 	sg_req[0].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_dma_memset()
916 	sg_req[0].ch_regs.csr = csr;  in tegra_dma_prep_dma_memset()
917 	sg_req[0].ch_regs.mmio_seq = 0;  in tegra_dma_prep_dma_memset()
918 	sg_req[0].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_dma_memset()
978 	sg_req[0].ch_regs.src_ptr = src;  in tegra_dma_prep_dma_memcpy()
979 	sg_req[0].ch_regs.dst_ptr = dest;  in tegra_dma_prep_dma_memcpy()
980 	sg_req[0].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_memcpy()
982 	sg_req[0].ch_regs.high_addr_ptr |=  in tegra_dma_prep_dma_memcpy()
985 	sg_req[0].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_dma_memcpy()
986 	sg_req[0].ch_regs.csr = csr;  in tegra_dma_prep_dma_memcpy()
987 	sg_req[0].ch_regs.mmio_seq = 0;  in tegra_dma_prep_dma_memcpy()
988 	sg_req[0].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_dma_memcpy()
1089 			sg_req[i].ch_regs.src_ptr = mem;  in tegra_dma_prep_slave_sg()
1090 			sg_req[i].ch_regs.dst_ptr = apb_ptr;  in tegra_dma_prep_slave_sg()
1091 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_slave_sg()
1094 			sg_req[i].ch_regs.src_ptr = apb_ptr;  in tegra_dma_prep_slave_sg()
1095 			sg_req[i].ch_regs.dst_ptr = mem;  in tegra_dma_prep_slave_sg()
1096 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_slave_sg()
1104 		sg_req[i].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_slave_sg()
1105 		sg_req[i].ch_regs.csr = csr;  in tegra_dma_prep_slave_sg()
1106 		sg_req[i].ch_regs.mmio_seq = mmio_seq;  in tegra_dma_prep_slave_sg()
1107 		sg_req[i].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_slave_sg()
1211 			sg_req[i].ch_regs.src_ptr = mem;  in tegra_dma_prep_dma_cyclic()
1212 			sg_req[i].ch_regs.dst_ptr = apb_ptr;  in tegra_dma_prep_dma_cyclic()
1213 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_cyclic()
1216 			sg_req[i].ch_regs.src_ptr = apb_ptr;  in tegra_dma_prep_dma_cyclic()
1217 			sg_req[i].ch_regs.dst_ptr = mem;  in tegra_dma_prep_dma_cyclic()
1218 			sg_req[i].ch_regs.high_addr_ptr =  in tegra_dma_prep_dma_cyclic()
1225 		sg_req[i].ch_regs.wcount = ((len - 4) >> 2);  in tegra_dma_prep_dma_cyclic()
1226 		sg_req[i].ch_regs.csr = csr;  in tegra_dma_prep_dma_cyclic()
1227 		sg_req[i].ch_regs.mmio_seq = mmio_seq;  in tegra_dma_prep_dma_cyclic()
1228 		sg_req[i].ch_regs.mc_seq = mc_seq;  in tegra_dma_prep_dma_cyclic()