Lines Matching refs:dmac
175 static void rz_dmac_writel(struct rz_dmac *dmac, unsigned int val, in rz_dmac_writel() argument
178 writel(val, dmac->base + offset); in rz_dmac_writel()
181 static void rz_dmac_ext_writel(struct rz_dmac *dmac, unsigned int val, in rz_dmac_ext_writel() argument
184 writel(val, dmac->ext_base + offset); in rz_dmac_ext_writel()
187 static u32 rz_dmac_ext_readl(struct rz_dmac *dmac, unsigned int offset) in rz_dmac_ext_readl() argument
189 return readl(dmac->ext_base + offset); in rz_dmac_ext_readl()
256 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_enable_hw() local
262 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); in rz_dmac_enable_hw()
287 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_disable_hw() local
290 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); in rz_dmac_disable_hw()
297 static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars) in rz_dmac_set_dmars_register() argument
303 dmars32 = rz_dmac_ext_readl(dmac, dmars_offset); in rz_dmac_set_dmars_register()
307 rz_dmac_ext_writel(dmac, dmars32, dmars_offset); in rz_dmac_set_dmars_register()
313 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_prepare_desc_for_memcpy() local
327 rz_dmac_set_dmars_register(dmac, channel->index, 0); in rz_dmac_prepare_desc_for_memcpy()
336 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_prepare_descs_for_slave_sg() local
378 rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); in rz_dmac_prepare_descs_for_slave_sg()
440 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_free_chan_resources() local
456 clear_bit(channel->mid_rid, dmac->modules); in rz_dmac_free_chan_resources()
476 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_prep_dma_memcpy() local
479 dev_dbg(dmac->dev, "%s channel: %d src=0x%pad dst=0x%pad len=%zu\n", in rz_dmac_prep_dma_memcpy()
553 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_issue_pending() local
565 dev_warn(dmac->dev, "ch: %d couldn't issue DMA xfer\n", in rz_dmac_issue_pending()
641 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_device_synchronize() local
648 dev_warn(dmac->dev, "DMA Timeout"); in rz_dmac_device_synchronize()
650 rz_dmac_set_dmars_register(dmac, channel->index, 0); in rz_dmac_device_synchronize()
661 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_irq_handle_channel() local
666 dev_err(dmac->dev, "DMAC err CHSTAT_%d = %08X\n", in rz_dmac_irq_handle_channel()
727 struct rz_dmac *dmac = to_rz_dmac(chan->device); in rz_dmac_chan_filter() local
736 return !test_and_set_bit(channel->mid_rid, dmac->modules); in rz_dmac_chan_filter()
759 static int rz_dmac_chan_probe(struct rz_dmac *dmac, in rz_dmac_chan_probe() argument
763 struct platform_device *pdev = to_platform_device(dmac->dev); in rz_dmac_chan_probe()
778 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u", in rz_dmac_chan_probe()
779 dev_name(dmac->dev), index); in rz_dmac_chan_probe()
783 ret = devm_request_threaded_irq(dmac->dev, channel->irq, in rz_dmac_chan_probe()
788 dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", in rz_dmac_chan_probe()
795 channel->ch_base = dmac->base + CHANNEL_0_7_OFFSET + in rz_dmac_chan_probe()
797 channel->ch_cmn_base = dmac->base + CHANNEL_0_7_COMMON_BASE; in rz_dmac_chan_probe()
799 channel->ch_base = dmac->base + CHANNEL_8_15_OFFSET + in rz_dmac_chan_probe()
801 channel->ch_cmn_base = dmac->base + CHANNEL_8_15_COMMON_BASE; in rz_dmac_chan_probe()
818 vchan_init(&channel->vc, &dmac->engine); in rz_dmac_chan_probe()
826 static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) in rz_dmac_parse_of() argument
831 ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels); in rz_dmac_parse_of()
837 if (!dmac->n_channels || dmac->n_channels > RZ_DMAC_MAX_CHANNELS) { in rz_dmac_parse_of()
838 dev_err(dev, "invalid number of channels %u\n", dmac->n_channels); in rz_dmac_parse_of()
849 struct rz_dmac *dmac; in rz_dmac_probe() local
855 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL); in rz_dmac_probe()
856 if (!dmac) in rz_dmac_probe()
859 dmac->dev = &pdev->dev; in rz_dmac_probe()
860 platform_set_drvdata(pdev, dmac); in rz_dmac_probe()
862 ret = rz_dmac_parse_of(&pdev->dev, dmac); in rz_dmac_probe()
866 dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels, in rz_dmac_probe()
867 sizeof(*dmac->channels), GFP_KERNEL); in rz_dmac_probe()
868 if (!dmac->channels) in rz_dmac_probe()
872 dmac->base = devm_platform_ioremap_resource(pdev, 0); in rz_dmac_probe()
873 if (IS_ERR(dmac->base)) in rz_dmac_probe()
874 return PTR_ERR(dmac->base); in rz_dmac_probe()
876 dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); in rz_dmac_probe()
877 if (IS_ERR(dmac->ext_base)) in rz_dmac_probe()
878 return PTR_ERR(dmac->ext_base); in rz_dmac_probe()
894 INIT_LIST_HEAD(&dmac->engine.channels); in rz_dmac_probe()
896 dmac->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); in rz_dmac_probe()
897 if (IS_ERR(dmac->rstc)) in rz_dmac_probe()
898 return dev_err_probe(&pdev->dev, PTR_ERR(dmac->rstc), in rz_dmac_probe()
908 ret = reset_control_deassert(dmac->rstc); in rz_dmac_probe()
912 for (i = 0; i < dmac->n_channels; i++) { in rz_dmac_probe()
913 ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i); in rz_dmac_probe()
925 engine = &dmac->engine; in rz_dmac_probe()
928 rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); in rz_dmac_probe()
929 rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); in rz_dmac_probe()
958 struct rz_dmac_chan *channel = &dmac->channels[i]; in rz_dmac_probe()
966 reset_control_assert(dmac->rstc); in rz_dmac_probe()
977 struct rz_dmac *dmac = platform_get_drvdata(pdev); in rz_dmac_remove() local
980 dma_async_device_unregister(&dmac->engine); in rz_dmac_remove()
982 for (i = 0; i < dmac->n_channels; i++) { in rz_dmac_remove()
983 struct rz_dmac_chan *channel = &dmac->channels[i]; in rz_dmac_remove()
990 reset_control_assert(dmac->rstc); in rz_dmac_remove()