Lines Matching +full:phy +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
21 #include <linux/dma/pxa-dma.h>
24 #include "virt-dma.h"
35 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
37 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
38 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
63 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
70 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
73 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
86 dma_addr_t first; /* First descriptor's addr */
91 struct dma_pool *desc_pool; /* Channel's used allocator */
106 enum pxad_chan_prio prio; /* Required priority of phy */
110 * setting on the phy.
115 /* protected by vc->lock */
116 struct pxad_phy *phy; member
129 spinlock_t phy_lock; /* Phy association */
145 #define _phy_readl_relaxed(phy, _reg) \ argument
146 readl_relaxed((phy)->base + _reg((phy)->idx))
147 #define phy_readl_relaxed(phy, _reg) \ argument
150 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
151 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
152 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \
156 #define phy_writel(phy, val, _reg) \ argument
158 writel((val), (phy)->base + _reg((phy)->idx)); \
159 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
160 "%s(): writel(0x%08x, %s)\n", \
163 #define phy_writel_relaxed(phy, val, _reg) \ argument
165 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
166 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
167 "%s(): writel_relaxed(0x%08x, %s)\n", \
188 static int requester_chan_show(struct seq_file *s, void *p) in requester_chan_show() argument
190 struct pxad_phy *phy = s->private; in requester_chan_show() local
194 seq_printf(s, "DMA channel %d requester :\n", phy->idx); in requester_chan_show()
196 drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); in requester_chan_show()
197 if ((drcmr & DRCMR_CHLNUM) == phy->idx) in requester_chan_show()
198 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i, in requester_chan_show()
219 static int descriptors_show(struct seq_file *s, void *p) in descriptors_show() argument
221 struct pxad_phy *phy = s->private; in descriptors_show() local
227 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR); in descriptors_show()
229 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx); in descriptors_show()
230 seq_printf(s, "[%03d] First descriptor unknown\n", 0); in descriptors_show()
233 dcmd = desc->dcmd; in descriptors_show()
237 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n", in descriptors_show()
239 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); in descriptors_show()
240 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); in descriptors_show()
241 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); in descriptors_show()
242 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", in descriptors_show()
249 phys_desc = desc->ddadr; in descriptors_show()
252 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", in descriptors_show()
255 seq_printf(s, "[%03d] Desc at %08lx is %s\n", in descriptors_show()
262 static int chan_state_show(struct seq_file *s, void *p) in chan_state_show() argument
264 struct pxad_phy *phy = s->private; in chan_state_show() local
271 dcsr = _phy_readl_relaxed(phy, DCSR); in chan_state_show()
272 dcmd = _phy_readl_relaxed(phy, DCMD); in chan_state_show()
276 seq_printf(s, "DMA channel %d\n", phy->idx); in chan_state_show()
277 seq_printf(s, "\tPriority : %s\n", in chan_state_show()
278 str_prio[(phy->idx & 0xf) / 4]); in chan_state_show()
279 seq_printf(s, "\tUnaligned transfer bit: %s\n", in chan_state_show()
280 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ? in chan_state_show()
282 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", in chan_state_show()
292 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", in chan_state_show()
298 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR)); in chan_state_show()
299 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR)); in chan_state_show()
300 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR)); in chan_state_show()
305 static int state_show(struct seq_file *s, void *p) in state_show() argument
307 struct pxad_device *pdev = s->private; in state_show()
310 seq_puts(s, "DMA engine status\n"); in state_show()
311 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans); in state_show()
330 dt = (void *)&pdev->phys[ch]; in pxad_dbg_alloc_chan()
344 pdev->dbgfs_chan = in pxad_init_debugfs()
345 kmalloc_array(pdev->nr_chans, sizeof(struct dentry *), in pxad_init_debugfs()
347 if (!pdev->dbgfs_chan) in pxad_init_debugfs()
350 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL); in pxad_init_debugfs()
352 debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops); in pxad_init_debugfs()
354 chandir = debugfs_create_dir("channels", pdev->dbgfs_root); in pxad_init_debugfs()
356 for (i = 0; i < pdev->nr_chans; i++) in pxad_init_debugfs()
357 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir); in pxad_init_debugfs()
362 debugfs_remove_recursive(pdev->dbgfs_root); in pxad_cleanup_debugfs()
372 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device); in lookup_phy()
373 struct pxad_phy *phy, *found = NULL; in lookup_phy() local
378 * ch 0 - 3, 16 - 19 <--> (0) in lookup_phy()
379 * ch 4 - 7, 20 - 23 <--> (1) in lookup_phy()
380 * ch 8 - 11, 24 - 27 <--> (2) in lookup_phy()
381 * ch 12 - 15, 28 - 31 <--> (3) in lookup_phy()
384 spin_lock_irqsave(&pdev->phy_lock, flags); in lookup_phy()
385 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) { in lookup_phy()
386 for (i = 0; i < pdev->nr_chans; i++) { in lookup_phy()
389 phy = &pdev->phys[i]; in lookup_phy()
390 if (!phy->vchan) { in lookup_phy()
391 phy->vchan = pchan; in lookup_phy()
392 found = phy; in lookup_phy()
399 spin_unlock_irqrestore(&pdev->phy_lock, flags); in lookup_phy()
400 dev_dbg(&pchan->vc.chan.dev->device, in lookup_phy()
401 "%s(): phy=%p(%d)\n", __func__, found, in lookup_phy()
402 found ? found->idx : -1); in lookup_phy()
409 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_free_phy()
413 dev_dbg(&chan->vc.chan.dev->device, in pxad_free_phy()
414 "%s(): freeing\n", __func__); in pxad_free_phy()
415 if (!chan->phy) in pxad_free_phy()
419 if (chan->drcmr <= pdev->nr_requestors) { in pxad_free_phy()
420 reg = pxad_drcmr(chan->drcmr); in pxad_free_phy()
421 writel_relaxed(0, chan->phy->base + reg); in pxad_free_phy()
424 spin_lock_irqsave(&pdev->phy_lock, flags); in pxad_free_phy()
425 chan->phy->vchan = NULL; in pxad_free_phy()
426 chan->phy = NULL; in pxad_free_phy()
427 spin_unlock_irqrestore(&pdev->phy_lock, flags); in pxad_free_phy()
433 struct pxad_phy *phy = chan->phy; in is_chan_running() local
435 if (!phy) in is_chan_running()
437 dcsr = phy_readl_relaxed(phy, DCSR); in is_chan_running()
445 BUG_ON(!chan->phy); in is_running_chan_misaligned()
446 dalgn = phy_readl_relaxed(chan->phy, DALGN); in is_running_chan_misaligned()
447 return dalgn & (BIT(chan->phy->idx)); in is_running_chan_misaligned()
450 static void phy_enable(struct pxad_phy *phy, bool misaligned) in phy_enable() argument
455 if (!phy->vchan) in phy_enable()
458 dev_dbg(&phy->vchan->vc.chan.dev->device, in phy_enable()
459 "%s(); phy=%p(%d) misaligned=%d\n", __func__, in phy_enable()
460 phy, phy->idx, misaligned); in phy_enable()
462 pdev = to_pxad_dev(phy->vchan->vc.chan.device); in phy_enable()
463 if (phy->vchan->drcmr <= pdev->nr_requestors) { in phy_enable()
464 reg = pxad_drcmr(phy->vchan->drcmr); in phy_enable()
465 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); in phy_enable()
468 dalgn = phy_readl_relaxed(phy, DALGN); in phy_enable()
470 dalgn |= BIT(phy->idx); in phy_enable()
472 dalgn &= ~BIT(phy->idx); in phy_enable()
473 phy_writel_relaxed(phy, dalgn, DALGN); in phy_enable()
475 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR | in phy_enable()
479 static void phy_disable(struct pxad_phy *phy) in phy_disable() argument
483 if (!phy) in phy_disable()
486 dcsr = phy_readl_relaxed(phy, DCSR); in phy_disable()
487 dev_dbg(&phy->vchan->vc.chan.dev->device, in phy_disable()
488 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx); in phy_disable()
489 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR); in phy_disable()
495 dev_dbg(&chan->vc.chan.dev->device, in pxad_launch_chan()
496 "%s(): desc=%p\n", __func__, desc); in pxad_launch_chan()
497 if (!chan->phy) { in pxad_launch_chan()
498 chan->phy = lookup_phy(chan); in pxad_launch_chan()
499 if (!chan->phy) { in pxad_launch_chan()
500 dev_dbg(&chan->vc.chan.dev->device, in pxad_launch_chan()
501 "%s(): no free dma channel\n", __func__); in pxad_launch_chan()
505 chan->bus_error = 0; in pxad_launch_chan()
508 * Program the descriptor's address into the DMA controller, in pxad_launch_chan()
511 phy_writel(chan->phy, desc->first, DDADR); in pxad_launch_chan()
512 phy_enable(chan->phy, chan->misaligned); in pxad_launch_chan()
513 wake_up(&chan->wq_state); in pxad_launch_chan()
520 sw_desc->hw_desc[sw_desc->nb_desc - 1]; in set_updater_desc()
521 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr; in set_updater_desc()
523 updater->ddadr = DDADR_STOP; in set_updater_desc()
524 updater->dsadr = dma; in set_updater_desc()
525 updater->dtadr = dma + 8; in set_updater_desc()
526 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 | in set_updater_desc()
529 updater->dcmd |= PXA_DCMD_ENDIRQEN; in set_updater_desc()
530 if (sw_desc->cyclic) in set_updater_desc()
531 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first; in set_updater_desc()
538 sw_desc->hw_desc[sw_desc->nb_desc - 1]; in is_desc_completed()
540 return updater->dtadr != (updater->dsadr + 8); in is_desc_completed()
550 dma_to_chain = desc2->first; in pxad_desc_chain()
551 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain; in pxad_desc_chain()
558 struct pxad_chan *chan = to_pxad_chan(&vc->chan); in pxad_try_hotchain()
561 * Attempt to hot chain the tx if the phy is still running. This is in pxad_try_hotchain()
568 BUG_ON(list_empty(&vc->desc_issued)); in pxad_try_hotchain()
571 to_pxad_sw_desc(vd)->misaligned) in pxad_try_hotchain()
574 vd_last_issued = list_entry(vc->desc_issued.prev, in pxad_try_hotchain()
584 static unsigned int clear_chan_irq(struct pxad_phy *phy) in clear_chan_irq() argument
587 u32 dint = readl(phy->base + DINT); in clear_chan_irq()
589 if (!(dint & BIT(phy->idx))) in clear_chan_irq()
593 dcsr = phy_readl_relaxed(phy, DCSR); in clear_chan_irq()
594 phy_writel(phy, dcsr, DCSR); in clear_chan_irq()
595 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) in clear_chan_irq()
596 dev_warn(&phy->vchan->vc.chan.dev->device, in clear_chan_irq()
597 "%s(chan=%p): PXA_DCSR_BUSERR\n", in clear_chan_irq()
598 __func__, &phy->vchan); in clear_chan_irq()
605 struct pxad_phy *phy = dev_id; in pxad_chan_handler() local
606 struct pxad_chan *chan = phy->vchan; in pxad_chan_handler()
614 dcsr = clear_chan_irq(phy); in pxad_chan_handler()
618 spin_lock(&chan->vc.lock); in pxad_chan_handler()
619 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { in pxad_chan_handler()
621 dev_dbg(&chan->vc.chan.dev->device, in pxad_chan_handler()
622 "%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n", in pxad_chan_handler()
623 __func__, vd, vd->tx.cookie, vd_completed, in pxad_chan_handler()
625 last_started = vd->tx.cookie; in pxad_chan_handler()
626 if (to_pxad_sw_desc(vd)->cyclic) { in pxad_chan_handler()
631 list_del(&vd->node); in pxad_chan_handler()
639 chan->bus_error = last_started; in pxad_chan_handler()
640 phy_disable(phy); in pxad_chan_handler()
643 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { in pxad_chan_handler()
644 dev_dbg(&chan->vc.chan.dev->device, in pxad_chan_handler()
645 "%s(): channel stopped, submitted_empty=%d issued_empty=%d", in pxad_chan_handler()
647 list_empty(&chan->vc.desc_submitted), in pxad_chan_handler()
648 list_empty(&chan->vc.desc_issued)); in pxad_chan_handler()
649 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR); in pxad_chan_handler()
651 if (list_empty(&chan->vc.desc_issued)) { in pxad_chan_handler()
652 chan->misaligned = in pxad_chan_handler()
653 !list_empty(&chan->vc.desc_submitted); in pxad_chan_handler()
655 vd = list_first_entry(&chan->vc.desc_issued, in pxad_chan_handler()
660 spin_unlock(&chan->vc.lock); in pxad_chan_handler()
661 wake_up(&chan->wq_state); in pxad_chan_handler()
669 struct pxad_phy *phy; in pxad_int_handler() local
670 u32 dint = readl(pdev->base + DINT); in pxad_int_handler()
675 dint &= (dint - 1); in pxad_int_handler()
676 phy = &pdev->phys[i]; in pxad_int_handler()
677 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED) in pxad_int_handler()
687 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_alloc_chan_resources()
689 if (chan->desc_pool) in pxad_alloc_chan_resources()
692 chan->desc_pool = dma_pool_create(dma_chan_name(dchan), in pxad_alloc_chan_resources()
693 pdev->slave.dev, in pxad_alloc_chan_resources()
697 if (!chan->desc_pool) { in pxad_alloc_chan_resources()
698 dev_err(&chan->vc.chan.dev->device, in pxad_alloc_chan_resources()
699 "%s(): unable to allocate descriptor pool\n", in pxad_alloc_chan_resources()
701 return -ENOMEM; in pxad_alloc_chan_resources()
711 vchan_free_chan_resources(&chan->vc); in pxad_free_chan_resources()
712 dma_pool_destroy(chan->desc_pool); in pxad_free_chan_resources()
713 chan->desc_pool = NULL; in pxad_free_chan_resources()
715 chan->drcmr = U32_MAX; in pxad_free_chan_resources()
716 chan->prio = PXAD_PRIO_LOWEST; in pxad_free_chan_resources()
725 for (i = sw_desc->nb_desc - 1; i >= 0; i--) { in pxad_free_desc()
727 dma = sw_desc->hw_desc[i - 1]->ddadr; in pxad_free_desc()
729 dma = sw_desc->first; in pxad_free_desc()
730 dma_pool_free(sw_desc->desc_pool, in pxad_free_desc()
731 sw_desc->hw_desc[i], dma); in pxad_free_desc()
733 sw_desc->nb_desc = 0; in pxad_free_desc()
749 sw_desc->desc_pool = chan->desc_pool; in pxad_alloc_desc()
752 desc = dma_pool_alloc(sw_desc->desc_pool, GFP_NOWAIT, &dma); in pxad_alloc_desc()
754 dev_err(&chan->vc.chan.dev->device, in pxad_alloc_desc()
755 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n", in pxad_alloc_desc()
756 __func__, i, sw_desc->desc_pool); in pxad_alloc_desc()
760 sw_desc->nb_desc++; in pxad_alloc_desc()
761 sw_desc->hw_desc[i] = desc; in pxad_alloc_desc()
764 sw_desc->first = dma; in pxad_alloc_desc()
766 sw_desc->hw_desc[i - 1]->ddadr = dma; in pxad_alloc_desc()
771 pxad_free_desc(&sw_desc->vd); in pxad_alloc_desc()
777 struct virt_dma_chan *vc = to_virt_chan(tx->chan); in pxad_tx_submit()
778 struct pxad_chan *chan = to_pxad_chan(&vc->chan); in pxad_tx_submit()
784 set_updater_desc(to_pxad_sw_desc(vd), tx->flags); in pxad_tx_submit()
786 spin_lock_irqsave(&vc->lock, flags); in pxad_tx_submit()
789 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { in pxad_tx_submit()
790 list_move_tail(&vd->node, &vc->desc_issued); in pxad_tx_submit()
791 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_submit()
792 "%s(): txd %p[%x]: submitted (hot linked)\n", in pxad_tx_submit()
800 if (!list_empty(&vc->desc_submitted)) { in pxad_tx_submit()
801 vd_chained = list_entry(vc->desc_submitted.prev, in pxad_tx_submit()
809 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) in pxad_tx_submit()
814 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_submit()
815 "%s(): txd %p[%x]: submitted (%s linked)\n", in pxad_tx_submit()
817 list_move_tail(&vd->node, &vc->desc_submitted); in pxad_tx_submit()
818 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; in pxad_tx_submit()
821 spin_unlock_irqrestore(&vc->lock, flags); in pxad_tx_submit()
831 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_issue_pending()
832 if (list_empty(&chan->vc.desc_submitted)) in pxad_issue_pending()
835 vd_first = list_first_entry(&chan->vc.desc_submitted, in pxad_issue_pending()
837 dev_dbg(&chan->vc.chan.dev->device, in pxad_issue_pending()
838 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); in pxad_issue_pending()
840 vchan_issue_pending(&chan->vc); in pxad_issue_pending()
841 if (!pxad_try_hotchain(&chan->vc, vd_first)) in pxad_issue_pending()
844 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_issue_pending()
854 INIT_LIST_HEAD(&vd->node); in pxad_tx_prep()
856 tx->tx_submit = pxad_tx_submit; in pxad_tx_prep()
857 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_prep()
858 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__, in pxad_tx_prep()
859 vc, vd, vd->tx.cookie, in pxad_tx_prep()
871 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_get_config()
875 maxburst = chan->cfg.src_maxburst; in pxad_get_config()
876 width = chan->cfg.src_addr_width; in pxad_get_config()
877 dev_addr = chan->cfg.src_addr; in pxad_get_config()
880 if (chan->drcmr <= pdev->nr_requestors) in pxad_get_config()
884 maxburst = chan->cfg.dst_maxburst; in pxad_get_config()
885 width = chan->cfg.dst_addr_width; in pxad_get_config()
886 dev_addr = chan->cfg.dst_addr; in pxad_get_config()
889 if (chan->drcmr <= pdev->nr_requestors) in pxad_get_config()
896 dev_dbg(&chan->vc.chan.dev->device, in pxad_get_config()
897 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n", in pxad_get_config()
930 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_memcpy()
931 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n", in pxad_prep_memcpy()
940 sw_desc->len = len; in pxad_prep_memcpy()
944 sw_desc->misaligned = true; in pxad_prep_memcpy()
948 hw_desc = sw_desc->hw_desc[i++]; in pxad_prep_memcpy()
950 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy); in pxad_prep_memcpy()
951 hw_desc->dsadr = dma_src; in pxad_prep_memcpy()
952 hw_desc->dtadr = dma_dst; in pxad_prep_memcpy()
953 len -= copy; in pxad_prep_memcpy()
959 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_memcpy()
979 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_slave_sg()
980 "%s(): dir=%d flags=%lx\n", __func__, dir, flags); in pxad_prep_slave_sg()
991 sw_desc->len += avail; in pxad_prep_slave_sg()
996 sw_desc->misaligned = true; in pxad_prep_slave_sg()
998 sw_desc->hw_desc[j]->dcmd = in pxad_prep_slave_sg()
1000 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma; in pxad_prep_slave_sg()
1001 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma; in pxad_prep_slave_sg()
1004 avail -= len; in pxad_prep_slave_sg()
1009 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_slave_sg()
1027 dev_err(&chan->vc.chan.dev->device, in pxad_prep_dma_cyclic()
1038 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_dma_cyclic()
1039 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n", in pxad_prep_dma_cyclic()
1047 sw_desc->cyclic = true; in pxad_prep_dma_cyclic()
1048 sw_desc->len = len; in pxad_prep_dma_cyclic()
1050 phw_desc = sw_desc->hw_desc; in pxad_prep_dma_cyclic()
1053 phw_desc[0]->dsadr = dsadr ? dsadr : dma; in pxad_prep_dma_cyclic()
1054 phw_desc[0]->dtadr = dtadr ? dtadr : dma; in pxad_prep_dma_cyclic()
1055 phw_desc[0]->dcmd = dcmd; in pxad_prep_dma_cyclic()
1058 len -= period_len; in pxad_prep_dma_cyclic()
1062 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_dma_cyclic()
1071 return -EINVAL; in pxad_config()
1073 chan->cfg = *cfg; in pxad_config()
1080 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_terminate_all()
1083 struct pxad_phy *phy; in pxad_terminate_all() local
1086 dev_dbg(&chan->vc.chan.dev->device, in pxad_terminate_all()
1087 "%s(): vchan %p: terminate all\n", __func__, &chan->vc); in pxad_terminate_all()
1089 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_terminate_all()
1090 vchan_get_all_descriptors(&chan->vc, &head); in pxad_terminate_all()
1093 dev_dbg(&chan->vc.chan.dev->device, in pxad_terminate_all()
1094 "%s(): cancelling txd %p[%x] (completed=%d)", __func__, in pxad_terminate_all()
1095 vd, vd->tx.cookie, is_desc_completed(vd)); in pxad_terminate_all()
1098 phy = chan->phy; in pxad_terminate_all()
1099 if (phy) { in pxad_terminate_all()
1100 phy_disable(chan->phy); in pxad_terminate_all()
1102 chan->phy = NULL; in pxad_terminate_all()
1103 spin_lock(&pdev->phy_lock); in pxad_terminate_all()
1104 phy->vchan = NULL; in pxad_terminate_all()
1105 spin_unlock(&pdev->phy_lock); in pxad_terminate_all()
1107 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_terminate_all()
1108 vchan_dma_desc_free_list(&chan->vc, &head); in pxad_terminate_all()
1125 * If the channel does not have a phy pointer anymore, it has already in pxad_residue()
1128 if (!chan->phy) in pxad_residue()
1131 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_residue()
1133 vd = vchan_find_desc(&chan->vc, cookie); in pxad_residue()
1138 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) in pxad_residue()
1139 curr = phy_readl_relaxed(chan->phy, DSADR); in pxad_residue()
1141 curr = phy_readl_relaxed(chan->phy, DTADR); in pxad_residue()
1153 for (i = 0; i < sw_desc->nb_desc - 1; i++) { in pxad_residue()
1154 hw_desc = sw_desc->hw_desc[i]; in pxad_residue()
1155 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) in pxad_residue()
1156 start = hw_desc->dsadr; in pxad_residue()
1158 start = hw_desc->dtadr; in pxad_residue()
1159 len = hw_desc->dcmd & PXA_DCMD_LENGTH; in pxad_residue()
1174 residue += end - curr; in pxad_residue()
1179 residue = sw_desc->len; in pxad_residue()
1182 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_residue()
1183 dev_dbg(&chan->vc.chan.dev->device, in pxad_residue()
1184 "%s(): txd %p[%x] sw_desc=%p: %d\n", in pxad_residue()
1196 if (cookie == chan->bus_error) in pxad_tx_status()
1210 wait_event(chan->wq_state, !is_chan_running(chan)); in pxad_synchronize()
1211 vchan_synchronize(&chan->vc); in pxad_synchronize()
1218 list_for_each_entry_safe(c, cn, &dmadev->channels, in pxad_free_channels()
1220 list_del(&c->vc.chan.device_node); in pxad_free_channels()
1221 tasklet_kill(&c->vc.task); in pxad_free_channels()
1230 pxad_free_channels(&pdev->slave); in pxad_remove()
1238 struct pxad_phy *phy; in pxad_init_phys() local
1244 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans, in pxad_init_phys()
1245 sizeof(pdev->phys[0]), GFP_KERNEL); in pxad_init_phys()
1246 if (!pdev->phys) in pxad_init_phys()
1247 return -ENOMEM; in pxad_init_phys()
1254 phy = &pdev->phys[i]; in pxad_init_phys()
1255 phy->base = pdev->base; in pxad_init_phys()
1256 phy->idx = i; in pxad_init_phys()
1259 ret = devm_request_irq(&op->dev, irq, in pxad_init_phys()
1261 IRQF_SHARED, "pxa-dma", phy); in pxad_init_phys()
1263 ret = devm_request_irq(&op->dev, irq0, in pxad_init_phys()
1265 IRQF_SHARED, "pxa-dma", pdev); in pxad_init_phys()
1267 dev_err(pdev->slave.dev, in pxad_init_phys()
1268 "%s(): can't request irq %d:%d\n", __func__, in pxad_init_phys()
1278 { .compatible = "marvell,pdma-1.0", },
1286 struct pxad_device *d = ofdma->of_dma_data; in pxad_dma_xlate()
1289 chan = dma_get_any_slave_channel(&d->slave); in pxad_dma_xlate()
1293 to_pxad_chan(chan)->drcmr = dma_spec->args[0]; in pxad_dma_xlate()
1294 to_pxad_chan(chan)->prio = dma_spec->args[1]; in pxad_dma_xlate()
1308 pdev->nr_chans = nr_phy_chans; in pxad_init_dmadev()
1309 pdev->nr_requestors = nr_requestors; in pxad_init_dmadev()
1310 INIT_LIST_HEAD(&pdev->slave.channels); in pxad_init_dmadev()
1311 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources; in pxad_init_dmadev()
1312 pdev->slave.device_free_chan_resources = pxad_free_chan_resources; in pxad_init_dmadev()
1313 pdev->slave.device_tx_status = pxad_tx_status; in pxad_init_dmadev()
1314 pdev->slave.device_issue_pending = pxad_issue_pending; in pxad_init_dmadev()
1315 pdev->slave.device_config = pxad_config; in pxad_init_dmadev()
1316 pdev->slave.device_synchronize = pxad_synchronize; in pxad_init_dmadev()
1317 pdev->slave.device_terminate_all = pxad_terminate_all; in pxad_init_dmadev()
1319 if (op->dev.coherent_dma_mask) in pxad_init_dmadev()
1320 dma_set_mask(&op->dev, op->dev.coherent_dma_mask); in pxad_init_dmadev()
1322 dma_set_mask(&op->dev, DMA_BIT_MASK(32)); in pxad_init_dmadev()
1329 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL); in pxad_init_dmadev()
1331 return -ENOMEM; in pxad_init_dmadev()
1333 c->drcmr = U32_MAX; in pxad_init_dmadev()
1334 c->prio = PXAD_PRIO_LOWEST; in pxad_init_dmadev()
1335 c->vc.desc_free = pxad_free_desc; in pxad_init_dmadev()
1336 vchan_init(&c->vc, &pdev->slave); in pxad_init_dmadev()
1337 init_waitqueue_head(&c->wq_state); in pxad_init_dmadev()
1340 return dmaenginem_async_device_register(&pdev->slave); in pxad_init_dmadev()
1347 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); in pxad_probe()
1353 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); in pxad_probe()
1355 return -ENOMEM; in pxad_probe()
1357 spin_lock_init(&pdev->phy_lock); in pxad_probe()
1359 pdev->base = devm_platform_ioremap_resource(op, 0); in pxad_probe()
1360 if (IS_ERR(pdev->base)) in pxad_probe()
1361 return PTR_ERR(pdev->base); in pxad_probe()
1363 if (op->dev.of_node) { in pxad_probe()
1364 /* Parse new and deprecated dma-channels properties */ in pxad_probe()
1365 if (of_property_read_u32(op->dev.of_node, "dma-channels", in pxad_probe()
1367 of_property_read_u32(op->dev.of_node, "#dma-channels", in pxad_probe()
1369 /* Parse new and deprecated dma-requests properties */ in pxad_probe()
1370 ret = of_property_read_u32(op->dev.of_node, "dma-requests", in pxad_probe()
1373 ret = of_property_read_u32(op->dev.of_node, "#dma-requests", in pxad_probe()
1376 dev_warn(pdev->slave.dev, in pxad_probe()
1377 "#dma-requests set to default 32 as missing in OF: %d", in pxad_probe()
1381 } else if (pdata && pdata->dma_channels) { in pxad_probe()
1382 dma_channels = pdata->dma_channels; in pxad_probe()
1383 nb_requestors = pdata->nb_requestors; in pxad_probe()
1384 slave_map = pdata->slave_map; in pxad_probe()
1385 slave_map_cnt = pdata->slave_map_cnt; in pxad_probe()
1390 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask); in pxad_probe()
1391 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask); in pxad_probe()
1392 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask); in pxad_probe()
1393 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask); in pxad_probe()
1394 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy; in pxad_probe()
1395 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg; in pxad_probe()
1396 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic; in pxad_probe()
1397 pdev->slave.filter.map = slave_map; in pxad_probe()
1398 pdev->slave.filter.mapcnt = slave_map_cnt; in pxad_probe()
1399 pdev->slave.filter.fn = pxad_filter_fn; in pxad_probe()
1401 pdev->slave.copy_align = PDMA_ALIGNMENT; in pxad_probe()
1402 pdev->slave.src_addr_widths = widths; in pxad_probe()
1403 pdev->slave.dst_addr_widths = widths; in pxad_probe()
1404 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); in pxad_probe()
1405 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in pxad_probe()
1406 pdev->slave.descriptor_reuse = true; in pxad_probe()
1408 pdev->slave.dev = &op->dev; in pxad_probe()
1411 dev_err(pdev->slave.dev, "unable to register\n"); in pxad_probe()
1415 if (op->dev.of_node) { in pxad_probe()
1416 /* Device-tree DMA controller registration */ in pxad_probe()
1417 ret = of_dma_controller_register(op->dev.of_node, in pxad_probe()
1420 dev_err(pdev->slave.dev, in pxad_probe()
1428 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n", in pxad_probe()
1434 { "pxa-dma", },
1440 .name = "pxa-dma",
1453 if (chan->device->dev->driver != &pxad_driver.driver) in pxad_filter_fn()
1456 c->drcmr = p->drcmr; in pxad_filter_fn()
1457 c->prio = p->prio; in pxad_filter_fn()