Lines Matching +full:asp +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013 - 2015 Linaro Ltd.
8 #include <linux/dma-mapping.h>
22 #include "virt-dma.h"
24 #define DRIVER_NAME "k3-dma"
138 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
140 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
142 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
144 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
154 val = 0x1 << phy->idx; in k3_dma_terminate_chan()
155 writel_relaxed(val, d->base + INT_TC1_RAW); in k3_dma_terminate_chan()
156 writel_relaxed(val, d->base + INT_TC2_RAW); in k3_dma_terminate_chan()
157 writel_relaxed(val, d->base + INT_ERR1_RAW); in k3_dma_terminate_chan()
158 writel_relaxed(val, d->base + INT_ERR2_RAW); in k3_dma_terminate_chan()
163 writel_relaxed(hw->lli, phy->base + CX_LLI); in k3_dma_set_desc()
164 writel_relaxed(hw->count, phy->base + CX_CNT0); in k3_dma_set_desc()
165 writel_relaxed(hw->saddr, phy->base + CX_SRC); in k3_dma_set_desc()
166 writel_relaxed(hw->daddr, phy->base + CX_DST); in k3_dma_set_desc()
167 writel_relaxed(hw->config, phy->base + CX_CFG); in k3_dma_set_desc()
174 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10); in k3_dma_get_curr_cnt()
181 return readl_relaxed(phy->base + CX_LLI); in k3_dma_get_curr_lli()
186 return readl_relaxed(d->base + CH_STAT); in k3_dma_get_chan_stat()
193 writel_relaxed(0x0, d->base + CH_PRI); in k3_dma_enable_dma()
196 writel_relaxed(0xffff, d->base + INT_TC1_MASK); in k3_dma_enable_dma()
197 writel_relaxed(0xffff, d->base + INT_TC2_MASK); in k3_dma_enable_dma()
198 writel_relaxed(0xffff, d->base + INT_ERR1_MASK); in k3_dma_enable_dma()
199 writel_relaxed(0xffff, d->base + INT_ERR2_MASK); in k3_dma_enable_dma()
202 writel_relaxed(0x0, d->base + INT_TC1_MASK); in k3_dma_enable_dma()
203 writel_relaxed(0x0, d->base + INT_TC2_MASK); in k3_dma_enable_dma()
204 writel_relaxed(0x0, d->base + INT_ERR1_MASK); in k3_dma_enable_dma()
205 writel_relaxed(0x0, d->base + INT_ERR2_MASK); in k3_dma_enable_dma()
214 u32 stat = readl_relaxed(d->base + INT_STAT); in k3_dma_int_handler()
215 u32 tc1 = readl_relaxed(d->base + INT_TC1); in k3_dma_int_handler()
216 u32 tc2 = readl_relaxed(d->base + INT_TC2); in k3_dma_int_handler()
217 u32 err1 = readl_relaxed(d->base + INT_ERR1); in k3_dma_int_handler()
218 u32 err2 = readl_relaxed(d->base + INT_ERR2); in k3_dma_int_handler()
226 p = &d->phy[i]; in k3_dma_int_handler()
227 c = p->vchan; in k3_dma_int_handler()
229 spin_lock(&c->vc.lock); in k3_dma_int_handler()
230 if (p->ds_run != NULL) { in k3_dma_int_handler()
231 vchan_cookie_complete(&p->ds_run->vd); in k3_dma_int_handler()
232 p->ds_done = p->ds_run; in k3_dma_int_handler()
233 p->ds_run = NULL; in k3_dma_int_handler()
235 spin_unlock(&c->vc.lock); in k3_dma_int_handler()
238 spin_lock(&c->vc.lock); in k3_dma_int_handler()
239 if (p->ds_run != NULL) in k3_dma_int_handler()
240 vchan_cyclic_callback(&p->ds_run->vd); in k3_dma_int_handler()
241 spin_unlock(&c->vc.lock); in k3_dma_int_handler()
246 dev_warn(d->slave.dev, "DMA ERR\n"); in k3_dma_int_handler()
249 writel_relaxed(irq_chan, d->base + INT_TC1_RAW); in k3_dma_int_handler()
250 writel_relaxed(irq_chan, d->base + INT_TC2_RAW); in k3_dma_int_handler()
251 writel_relaxed(err1, d->base + INT_ERR1_RAW); in k3_dma_int_handler()
252 writel_relaxed(err2, d->base + INT_ERR2_RAW); in k3_dma_int_handler()
255 tasklet_schedule(&d->task); in k3_dma_int_handler()
265 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device); in k3_dma_start_txd()
266 struct virt_dma_desc *vd = vchan_next_desc(&c->vc); in k3_dma_start_txd()
268 if (!c->phy) in k3_dma_start_txd()
269 return -EAGAIN; in k3_dma_start_txd()
271 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d)) in k3_dma_start_txd()
272 return -EAGAIN; in k3_dma_start_txd()
275 if (c->phy->ds_run) in k3_dma_start_txd()
276 return -EAGAIN; in k3_dma_start_txd()
282 * fetch and remove request from vc->desc_issued in k3_dma_start_txd()
283 * so vc->desc_issued only contains desc pending in k3_dma_start_txd()
285 list_del(&ds->vd.node); in k3_dma_start_txd()
287 c->phy->ds_run = ds; in k3_dma_start_txd()
288 c->phy->ds_done = NULL; in k3_dma_start_txd()
290 k3_dma_set_desc(c->phy, &ds->desc_hw[0]); in k3_dma_start_txd()
293 c->phy->ds_run = NULL; in k3_dma_start_txd()
294 c->phy->ds_done = NULL; in k3_dma_start_txd()
295 return -EAGAIN; in k3_dma_start_txd()
305 /* check new dma request of running channel in vc->desc_issued */ in k3_dma_tasklet()
306 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) { in k3_dma_tasklet()
307 spin_lock_irq(&c->vc.lock); in k3_dma_tasklet()
308 p = c->phy; in k3_dma_tasklet()
309 if (p && p->ds_done) { in k3_dma_tasklet()
312 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx); in k3_dma_tasklet()
314 c->phy = NULL; in k3_dma_tasklet()
315 p->vchan = NULL; in k3_dma_tasklet()
318 spin_unlock_irq(&c->vc.lock); in k3_dma_tasklet()
321 /* check new channel request in d->chan_pending */ in k3_dma_tasklet()
322 spin_lock_irq(&d->lock); in k3_dma_tasklet()
323 for (pch = 0; pch < d->dma_channels; pch++) { in k3_dma_tasklet()
324 if (!(d->dma_channel_mask & (1 << pch))) in k3_dma_tasklet()
327 p = &d->phy[pch]; in k3_dma_tasklet()
329 if (p->vchan == NULL && !list_empty(&d->chan_pending)) { in k3_dma_tasklet()
330 c = list_first_entry(&d->chan_pending, in k3_dma_tasklet()
332 /* remove from d->chan_pending */ in k3_dma_tasklet()
333 list_del_init(&c->node); in k3_dma_tasklet()
336 p->vchan = c; in k3_dma_tasklet()
337 c->phy = p; in k3_dma_tasklet()
338 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc); in k3_dma_tasklet()
341 spin_unlock_irq(&d->lock); in k3_dma_tasklet()
343 for (pch = 0; pch < d->dma_channels; pch++) { in k3_dma_tasklet()
344 if (!(d->dma_channel_mask & (1 << pch))) in k3_dma_tasklet()
348 p = &d->phy[pch]; in k3_dma_tasklet()
349 c = p->vchan; in k3_dma_tasklet()
351 spin_lock_irq(&c->vc.lock); in k3_dma_tasklet()
353 spin_unlock_irq(&c->vc.lock); in k3_dma_tasklet()
362 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_free_chan_resources()
365 spin_lock_irqsave(&d->lock, flags); in k3_dma_free_chan_resources()
366 list_del_init(&c->node); in k3_dma_free_chan_resources()
367 spin_unlock_irqrestore(&d->lock, flags); in k3_dma_free_chan_resources()
369 vchan_free_chan_resources(&c->vc); in k3_dma_free_chan_resources()
370 c->ccfg = 0; in k3_dma_free_chan_resources()
377 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_tx_status()
384 ret = dma_cookie_status(&c->vc.chan, cookie, state); in k3_dma_tx_status()
388 spin_lock_irqsave(&c->vc.lock, flags); in k3_dma_tx_status()
389 p = c->phy; in k3_dma_tx_status()
390 ret = c->status; in k3_dma_tx_status()
396 vd = vchan_find_desc(&c->vc, cookie); in k3_dma_tx_status()
397 if (vd && !c->cyclic) { in k3_dma_tx_status()
398 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size; in k3_dma_tx_status()
399 } else if ((!p) || (!p->ds_run)) { in k3_dma_tx_status()
402 struct k3_dma_desc_sw *ds = p->ds_run; in k3_dma_tx_status()
407 index = ((clli - ds->desc_hw_lli) / in k3_dma_tx_status()
409 for (; index < ds->desc_num; index++) { in k3_dma_tx_status()
410 bytes += ds->desc_hw[index].count; in k3_dma_tx_status()
412 if (!ds->desc_hw[index].lli) in k3_dma_tx_status()
416 spin_unlock_irqrestore(&c->vc.lock, flags); in k3_dma_tx_status()
424 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_issue_pending()
427 spin_lock_irqsave(&c->vc.lock, flags); in k3_dma_issue_pending()
428 /* add request to vc->desc_issued */ in k3_dma_issue_pending()
429 if (vchan_issue_pending(&c->vc)) { in k3_dma_issue_pending()
430 spin_lock(&d->lock); in k3_dma_issue_pending()
431 if (!c->phy) { in k3_dma_issue_pending()
432 if (list_empty(&c->node)) { in k3_dma_issue_pending()
434 list_add_tail(&c->node, &d->chan_pending); in k3_dma_issue_pending()
436 tasklet_schedule(&d->task); in k3_dma_issue_pending()
437 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc); in k3_dma_issue_pending()
440 spin_unlock(&d->lock); in k3_dma_issue_pending()
442 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc); in k3_dma_issue_pending()
443 spin_unlock_irqrestore(&c->vc.lock, flags); in k3_dma_issue_pending()
449 if (num != ds->desc_num - 1) in k3_dma_fill_desc()
450 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) * in k3_dma_fill_desc()
453 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN; in k3_dma_fill_desc()
454 ds->desc_hw[num].count = len; in k3_dma_fill_desc()
455 ds->desc_hw[num].saddr = src; in k3_dma_fill_desc()
456 ds->desc_hw[num].daddr = dst; in k3_dma_fill_desc()
457 ds->desc_hw[num].config = ccfg; in k3_dma_fill_desc()
465 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_alloc_desc_resource()
469 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n", in k3_dma_alloc_desc_resource()
470 &c->vc, num, lli_limit); in k3_dma_alloc_desc_resource()
478 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli); in k3_dma_alloc_desc_resource()
479 if (!ds->desc_hw) { in k3_dma_alloc_desc_resource()
480 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc); in k3_dma_alloc_desc_resource()
484 ds->desc_num = num; in k3_dma_alloc_desc_resource()
506 c->cyclic = 0; in k3_dma_prep_memcpy()
507 ds->size = len; in k3_dma_prep_memcpy()
510 if (!c->ccfg) { in k3_dma_prep_memcpy()
512 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN; in k3_dma_prep_memcpy()
513 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */ in k3_dma_prep_memcpy()
514 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */ in k3_dma_prep_memcpy()
519 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg); in k3_dma_prep_memcpy()
523 len -= copy; in k3_dma_prep_memcpy()
526 ds->desc_hw[num-1].lli = 0; /* end of link */ in k3_dma_prep_memcpy()
527 return vchan_tx_prep(&c->vc, &ds->vd, flags); in k3_dma_prep_memcpy()
544 c->cyclic = 0; in k3_dma_prep_slave_sg()
549 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1; in k3_dma_prep_slave_sg()
556 k3_dma_config_write(chan, dir, &c->slave_config); in k3_dma_prep_slave_sg()
568 dst = c->dev_addr; in k3_dma_prep_slave_sg()
570 src = c->dev_addr; in k3_dma_prep_slave_sg()
574 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg); in k3_dma_prep_slave_sg()
577 avail -= len; in k3_dma_prep_slave_sg()
581 ds->desc_hw[num-1].lli = 0; /* end of link */ in k3_dma_prep_slave_sg()
582 ds->size = total; in k3_dma_prep_slave_sg()
583 return vchan_tx_prep(&c->vc, &ds->vd, flags); in k3_dma_prep_slave_sg()
600 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n", in k3_dma_prep_dma_cyclic()
601 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr, in k3_dma_prep_dma_cyclic()
606 num += DIV_ROUND_UP(avail, modulo) - 1; in k3_dma_prep_dma_cyclic()
612 c->cyclic = 1; in k3_dma_prep_dma_cyclic()
617 k3_dma_config_write(chan, dir, &c->slave_config); in k3_dma_prep_dma_cyclic()
627 dst = c->dev_addr; in k3_dma_prep_dma_cyclic()
629 src = c->dev_addr; in k3_dma_prep_dma_cyclic()
636 since -= period_len; in k3_dma_prep_dma_cyclic()
640 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2); in k3_dma_prep_dma_cyclic()
643 avail -= len; in k3_dma_prep_dma_cyclic()
647 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli; in k3_dma_prep_dma_cyclic()
649 ds->size = total; in k3_dma_prep_dma_cyclic()
651 return vchan_tx_prep(&c->vc, &ds->vd, flags); in k3_dma_prep_dma_cyclic()
659 memcpy(&c->slave_config, cfg, sizeof(*cfg)); in k3_dma_config()
673 c->ccfg = CX_CFG_DSTINCR; in k3_dma_config_write()
674 c->dev_addr = cfg->src_addr; in k3_dma_config_write()
675 maxburst = cfg->src_maxburst; in k3_dma_config_write()
676 width = cfg->src_addr_width; in k3_dma_config_write()
678 c->ccfg = CX_CFG_SRCINCR; in k3_dma_config_write()
679 c->dev_addr = cfg->dst_addr; in k3_dma_config_write()
680 maxburst = cfg->dst_maxburst; in k3_dma_config_write()
681 width = cfg->dst_addr_width; in k3_dma_config_write()
694 c->ccfg |= (val << 12) | (val << 16); in k3_dma_config_write()
699 val = maxburst - 1; in k3_dma_config_write()
700 c->ccfg |= (val << 20) | (val << 24); in k3_dma_config_write()
701 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN; in k3_dma_config_write()
704 c->ccfg |= c->vc.chan.chan_id << 4; in k3_dma_config_write()
713 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device); in k3_dma_free_desc()
715 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli); in k3_dma_free_desc()
722 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_terminate_all()
723 struct k3_dma_phy *p = c->phy; in k3_dma_terminate_all()
727 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc); in k3_dma_terminate_all()
730 spin_lock(&d->lock); in k3_dma_terminate_all()
731 list_del_init(&c->node); in k3_dma_terminate_all()
732 spin_unlock(&d->lock); in k3_dma_terminate_all()
735 spin_lock_irqsave(&c->vc.lock, flags); in k3_dma_terminate_all()
736 vchan_get_all_descriptors(&c->vc, &head); in k3_dma_terminate_all()
738 /* vchan is assigned to a pchan - stop the channel */ in k3_dma_terminate_all()
740 c->phy = NULL; in k3_dma_terminate_all()
741 p->vchan = NULL; in k3_dma_terminate_all()
742 if (p->ds_run) { in k3_dma_terminate_all()
743 vchan_terminate_vdesc(&p->ds_run->vd); in k3_dma_terminate_all()
744 p->ds_run = NULL; in k3_dma_terminate_all()
746 p->ds_done = NULL; in k3_dma_terminate_all()
748 spin_unlock_irqrestore(&c->vc.lock, flags); in k3_dma_terminate_all()
749 vchan_dma_desc_free_list(&c->vc, &head); in k3_dma_terminate_all()
758 vchan_synchronize(&c->vc); in k3_dma_synchronize()
764 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_transfer_pause()
765 struct k3_dma_phy *p = c->phy; in k3_dma_transfer_pause()
767 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc); in k3_dma_transfer_pause()
768 if (c->status == DMA_IN_PROGRESS) { in k3_dma_transfer_pause()
769 c->status = DMA_PAUSED; in k3_dma_transfer_pause()
773 spin_lock(&d->lock); in k3_dma_transfer_pause()
774 list_del_init(&c->node); in k3_dma_transfer_pause()
775 spin_unlock(&d->lock); in k3_dma_transfer_pause()
785 struct k3_dma_dev *d = to_k3_dma(chan->device); in k3_dma_transfer_resume()
786 struct k3_dma_phy *p = c->phy; in k3_dma_transfer_resume()
789 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc); in k3_dma_transfer_resume()
790 spin_lock_irqsave(&c->vc.lock, flags); in k3_dma_transfer_resume()
791 if (c->status == DMA_PAUSED) { in k3_dma_transfer_resume()
792 c->status = DMA_IN_PROGRESS; in k3_dma_transfer_resume()
795 } else if (!list_empty(&c->vc.desc_issued)) { in k3_dma_transfer_resume()
796 spin_lock(&d->lock); in k3_dma_transfer_resume()
797 list_add_tail(&c->node, &d->chan_pending); in k3_dma_transfer_resume()
798 spin_unlock(&d->lock); in k3_dma_transfer_resume()
801 spin_unlock_irqrestore(&c->vc.lock, flags); in k3_dma_transfer_resume()
815 { .compatible = "hisilicon,k3-dma-1.0",
818 { .compatible = "hisilicon,hisi-pcm-asp-dma-1.0",
828 struct k3_dma_dev *d = ofdma->of_dma_data; in k3_of_dma_simple_xlate()
829 unsigned int request = dma_spec->args[0]; in k3_of_dma_simple_xlate()
831 if (request >= d->dma_requests) in k3_of_dma_simple_xlate()
834 return dma_get_slave_channel(&(d->chans[request].vc.chan)); in k3_of_dma_simple_xlate()
843 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL); in k3_dma_probe()
845 return -ENOMEM; in k3_dma_probe()
847 soc_data = device_get_match_data(&op->dev); in k3_dma_probe()
849 return -EINVAL; in k3_dma_probe()
851 d->base = devm_platform_ioremap_resource(op, 0); in k3_dma_probe()
852 if (IS_ERR(d->base)) in k3_dma_probe()
853 return PTR_ERR(d->base); in k3_dma_probe()
855 of_property_read_u32((&op->dev)->of_node, in k3_dma_probe()
856 "dma-channels", &d->dma_channels); in k3_dma_probe()
857 of_property_read_u32((&op->dev)->of_node, in k3_dma_probe()
858 "dma-requests", &d->dma_requests); in k3_dma_probe()
859 ret = of_property_read_u32((&op->dev)->of_node, in k3_dma_probe()
860 "dma-channel-mask", &d->dma_channel_mask); in k3_dma_probe()
862 dev_warn(&op->dev, in k3_dma_probe()
863 "dma-channel-mask doesn't exist, considering all as available.\n"); in k3_dma_probe()
864 d->dma_channel_mask = (u32)~0UL; in k3_dma_probe()
867 if (!(soc_data->flags & K3_FLAG_NOCLK)) { in k3_dma_probe()
868 d->clk = devm_clk_get(&op->dev, NULL); in k3_dma_probe()
869 if (IS_ERR(d->clk)) { in k3_dma_probe()
870 dev_err(&op->dev, "no dma clk\n"); in k3_dma_probe()
871 return PTR_ERR(d->clk); in k3_dma_probe()
876 ret = devm_request_irq(&op->dev, irq, in k3_dma_probe()
881 d->irq = irq; in k3_dma_probe()
883 /* A DMA memory pool for LLIs, align on 32-byte boundary */ in k3_dma_probe()
884 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev, in k3_dma_probe()
886 if (!d->pool) in k3_dma_probe()
887 return -ENOMEM; in k3_dma_probe()
890 d->phy = devm_kcalloc(&op->dev, in k3_dma_probe()
891 d->dma_channels, sizeof(struct k3_dma_phy), GFP_KERNEL); in k3_dma_probe()
892 if (d->phy == NULL) in k3_dma_probe()
893 return -ENOMEM; in k3_dma_probe()
895 for (i = 0; i < d->dma_channels; i++) { in k3_dma_probe()
898 if (!(d->dma_channel_mask & BIT(i))) in k3_dma_probe()
901 p = &d->phy[i]; in k3_dma_probe()
902 p->idx = i; in k3_dma_probe()
903 p->base = d->base + i * 0x40; in k3_dma_probe()
906 INIT_LIST_HEAD(&d->slave.channels); in k3_dma_probe()
907 dma_cap_set(DMA_SLAVE, d->slave.cap_mask); in k3_dma_probe()
908 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask); in k3_dma_probe()
909 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask); in k3_dma_probe()
910 d->slave.dev = &op->dev; in k3_dma_probe()
911 d->slave.device_free_chan_resources = k3_dma_free_chan_resources; in k3_dma_probe()
912 d->slave.device_tx_status = k3_dma_tx_status; in k3_dma_probe()
913 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy; in k3_dma_probe()
914 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg; in k3_dma_probe()
915 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic; in k3_dma_probe()
916 d->slave.device_issue_pending = k3_dma_issue_pending; in k3_dma_probe()
917 d->slave.device_config = k3_dma_config; in k3_dma_probe()
918 d->slave.device_pause = k3_dma_transfer_pause; in k3_dma_probe()
919 d->slave.device_resume = k3_dma_transfer_resume; in k3_dma_probe()
920 d->slave.device_terminate_all = k3_dma_terminate_all; in k3_dma_probe()
921 d->slave.device_synchronize = k3_dma_synchronize; in k3_dma_probe()
922 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES; in k3_dma_probe()
925 d->chans = devm_kcalloc(&op->dev, in k3_dma_probe()
926 d->dma_requests, sizeof(struct k3_dma_chan), GFP_KERNEL); in k3_dma_probe()
927 if (d->chans == NULL) in k3_dma_probe()
928 return -ENOMEM; in k3_dma_probe()
930 for (i = 0; i < d->dma_requests; i++) { in k3_dma_probe()
931 struct k3_dma_chan *c = &d->chans[i]; in k3_dma_probe()
933 c->status = DMA_IN_PROGRESS; in k3_dma_probe()
934 INIT_LIST_HEAD(&c->node); in k3_dma_probe()
935 c->vc.desc_free = k3_dma_free_desc; in k3_dma_probe()
936 vchan_init(&c->vc, &d->slave); in k3_dma_probe()
940 ret = clk_prepare_enable(d->clk); in k3_dma_probe()
942 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret); in k3_dma_probe()
948 ret = dma_async_device_register(&d->slave); in k3_dma_probe()
952 ret = of_dma_controller_register((&op->dev)->of_node, in k3_dma_probe()
957 spin_lock_init(&d->lock); in k3_dma_probe()
958 INIT_LIST_HEAD(&d->chan_pending); in k3_dma_probe()
959 tasklet_setup(&d->task, k3_dma_tasklet); in k3_dma_probe()
961 dev_info(&op->dev, "initialized\n"); in k3_dma_probe()
966 dma_async_device_unregister(&d->slave); in k3_dma_probe()
968 clk_disable_unprepare(d->clk); in k3_dma_probe()
977 dma_async_device_unregister(&d->slave); in k3_dma_remove()
978 of_dma_controller_free((&op->dev)->of_node); in k3_dma_remove()
980 devm_free_irq(&op->dev, d->irq, d); in k3_dma_remove()
982 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) { in k3_dma_remove()
983 list_del(&c->vc.chan.device_node); in k3_dma_remove()
984 tasklet_kill(&c->vc.task); in k3_dma_remove()
986 tasklet_kill(&d->task); in k3_dma_remove()
987 clk_disable_unprepare(d->clk); in k3_dma_remove()
998 dev_warn(d->slave.dev, in k3_dma_suspend_dev()
1000 return -1; in k3_dma_suspend_dev()
1003 clk_disable_unprepare(d->clk); in k3_dma_suspend_dev()
1012 ret = clk_prepare_enable(d->clk); in k3_dma_resume_dev()
1014 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret); in k3_dma_resume_dev()
1038 MODULE_LICENSE("GPL v2");