1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define GET_IDXD_VER_MAJOR(x)		(((x) & IDXD_VER_MAJOR_MASK) >> 4)
37 		u64 max_batch_shift:4;
42 	u64 bits;  member
50 		u64 wqcfg_size:4;
62 	u64 bits;  member
76 	u64 bits;  member
85 	u64 bits;  member
94 	u64 bits[4];  member
111 	u64 bits[2];  member
120 		u32 rsvd:4;
125 	u32 bits;  member
136 	u32 bits;  member
146 	u32 bits;  member
180 	u32 bits;  member
210 	u32 bits;  member
271 		u64 rsvd3:4;
281 	u64 bits[4];  member
300 	u64 bits;  member
317 	u64 bits[2];  member
331 	u32 bits;  member
341 		u64 rsvd2:4;
343 		u64 rsvd3:4;
349 	u64 bits;  member
353 	u64 wqs[4];
360 		/* bytes 0-3 */
364 		/* bytes 4-7 */
368 		/* bytes 8-11 */
373 		u32 priority:4;
379 		/* bytes 12-15 */
381 		u32 max_batch_shift:4;
384 		/* bytes 16-19 */
389 		/* bytes 20-23 */
394 		/* bytes 24-27 */
401 		/* bytes 28-31 */
404 		/* bytes 32-63 */
405 		u64 op_config[4];
407 	u32 bits[16];  member
418  * idxd - struct idxd *
419  * n - wq id
420  * ofs - the index of the 32b dword for the config register
424  * Each register is 32bits. The ofs gives us the number of register to access.
429 	(__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs);	\
432 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
435 #define GRPWQCFG_STRIDES	4
439  * idxd - struct idxd *
440  * n - group id
441  * ofs - the index of the 64b qword for the config register
443  * The GRPCFG register block is divided into three sub-registers, which
445  * to the register block that contains the three sub-registers.
446  * Each register block is 64bits. And the ofs gives us the offset
449 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
451 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32)
452 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40)
461 		u64 num_event_category:4;
471 	u64 bits;  member
480 	u64 bits;  member
486 			u32 event_category:4;
499 			u32 num_events:4;
525 		u64 event_category:4;
528 		u64 rsvd3:4;
545 		u64 event_cat:4;
555 		u64 pg_sz:4;
577 	u64 bits;  member
595 	u64 rsvd2:4;
627 	u64 rsvd[4];