Lines Matching +full:common +full:- +full:mode +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
18 * command. Please be aware that this setting may result in read pre-fetching
29 #include <linux/dma-mapping.h>
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
52 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); in set_sr()
57 return FSL_DMA_IN(chan, &chan->regs->sr, 32); in get_sr()
62 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); in set_mr()
67 return FSL_DMA_IN(chan, &chan->regs->mr, 32); in get_mr()
72 FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); in set_cdar()
77 return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; in get_cdar()
82 FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32); in set_bcr()
87 return FSL_DMA_IN(chan, &chan->regs->bcr, 32); in get_bcr()
97 hw->count = CPU_TO_DMA(chan, count, 32); in set_desc_cnt()
105 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) in set_desc_src()
107 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); in set_desc_src()
115 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) in set_desc_dst()
117 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); in set_desc_dst()
125 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) in set_desc_next()
127 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); in set_desc_next()
134 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) in set_ld_eol()
137 desc->hw.next_ln_addr = CPU_TO_DMA(chan, in set_ld_eol()
138 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL in set_ld_eol()
148 /* Reset the channel */ in dma_init()
151 switch (chan->feature & FSL_DMA_IP_MASK) { in dma_init()
153 /* Set the channel to below modes: in dma_init()
154 * EIE - Error interrupt enable in dma_init()
155 * EOLNIE - End of links interrupt enable in dma_init()
156 * BWC - Bandwidth sharing among channels in dma_init()
162 /* Set the channel to below modes: in dma_init()
163 * EOTIE - End-of-transfer interrupt enable in dma_init()
164 * PRC_RM - PCI read multiple in dma_init()
181 * - the CDAR register must point to the start descriptor
182 * - the MRn[CS] bit must be cleared
186 u32 mode; in dma_start() local
188 mode = get_mr(chan); in dma_start()
190 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { in dma_start()
192 mode |= FSL_DMA_MR_EMP_EN; in dma_start()
194 mode &= ~FSL_DMA_MR_EMP_EN; in dma_start()
197 if (chan->feature & FSL_DMA_CHAN_START_EXT) { in dma_start()
198 mode |= FSL_DMA_MR_EMS_EN; in dma_start()
200 mode &= ~FSL_DMA_MR_EMS_EN; in dma_start()
201 mode |= FSL_DMA_MR_CS; in dma_start()
204 set_mr(chan, mode); in dma_start()
209 u32 mode; in dma_halt() local
212 /* read the mode register */ in dma_halt()
213 mode = get_mr(chan); in dma_halt()
216 * The 85xx controller supports channel abort, which will stop in dma_halt()
220 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { in dma_halt()
221 mode |= FSL_DMA_MR_CA; in dma_halt()
222 set_mr(chan, mode); in dma_halt()
224 mode &= ~FSL_DMA_MR_CA; in dma_halt()
228 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); in dma_halt()
229 set_mr(chan, mode); in dma_halt()
244 * fsl_chan_set_src_loop_size - Set source address hold transfer size
245 * @chan : Freescale DMA channel
256 u32 mode; in fsl_chan_set_src_loop_size() local
258 mode = get_mr(chan); in fsl_chan_set_src_loop_size()
262 mode &= ~FSL_DMA_MR_SAHE; in fsl_chan_set_src_loop_size()
268 mode &= ~FSL_DMA_MR_SAHTS_MASK; in fsl_chan_set_src_loop_size()
269 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); in fsl_chan_set_src_loop_size()
273 set_mr(chan, mode); in fsl_chan_set_src_loop_size()
277 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
278 * @chan : Freescale DMA channel
289 u32 mode; in fsl_chan_set_dst_loop_size() local
291 mode = get_mr(chan); in fsl_chan_set_dst_loop_size()
295 mode &= ~FSL_DMA_MR_DAHE; in fsl_chan_set_dst_loop_size()
301 mode &= ~FSL_DMA_MR_DAHTS_MASK; in fsl_chan_set_dst_loop_size()
302 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); in fsl_chan_set_dst_loop_size()
306 set_mr(chan, mode); in fsl_chan_set_dst_loop_size()
310 * fsl_chan_set_request_count - Set DMA Request Count for external control
311 * @chan : Freescale DMA channel
314 * The Freescale DMA channel can be controlled by the external signal DREQ#.
316 * pausing the channel, after which a new assertion of DREQ# resumes channel
323 u32 mode; in fsl_chan_set_request_count() local
327 mode = get_mr(chan); in fsl_chan_set_request_count()
328 mode &= ~FSL_DMA_MR_BWC_MASK; in fsl_chan_set_request_count()
329 mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK; in fsl_chan_set_request_count()
331 set_mr(chan, mode); in fsl_chan_set_request_count()
335 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
336 * @chan : Freescale DMA channel
339 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * to set the number of bytes to transfer before pausing the channel.
346 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; in fsl_chan_toggle_ext_pause()
348 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; in fsl_chan_toggle_ext_pause()
352 * fsl_chan_toggle_ext_start - Toggle channel external start status
353 * @chan : Freescale DMA channel
356 * If enable the external start, the channel can be started by an
358 * transfer immediately. The DMA channel will wait for the
364 chan->feature |= FSL_DMA_CHAN_START_EXT; in fsl_chan_toggle_ext_start()
366 chan->feature &= ~FSL_DMA_CHAN_START_EXT; in fsl_chan_toggle_ext_start()
374 return -EINVAL; in fsl_dma_external_start()
385 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); in append_ld_queue()
387 if (list_empty(&chan->ld_pending)) in append_ld_queue()
394 * This will un-set the EOL bit of the existing transaction, and the in append_ld_queue()
397 set_desc_next(chan, &tail->hw, desc->async_tx.phys); in append_ld_queue()
404 list_splice_tail_init(&desc->tx_list, &chan->ld_pending); in append_ld_queue()
409 struct fsldma_chan *chan = to_fsl_chan(tx->chan); in fsl_dma_tx_submit()
412 dma_cookie_t cookie = -EINVAL; in fsl_dma_tx_submit()
414 spin_lock_bh(&chan->desc_lock); in fsl_dma_tx_submit()
417 if (unlikely(chan->pm_state != RUNNING)) { in fsl_dma_tx_submit()
419 spin_unlock_bh(&chan->desc_lock); in fsl_dma_tx_submit()
420 return -1; in fsl_dma_tx_submit()
428 list_for_each_entry(child, &desc->tx_list, node) { in fsl_dma_tx_submit()
429 cookie = dma_cookie_assign(&child->async_tx); in fsl_dma_tx_submit()
435 spin_unlock_bh(&chan->desc_lock); in fsl_dma_tx_submit()
441 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
442 * @chan : Freescale DMA channel
448 list_del(&desc->node); in fsl_dma_free_descriptor()
450 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); in fsl_dma_free_descriptor()
454 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
455 * @chan : Freescale DMA channel
457 * Return - The descriptor allocated. NULL for failed.
464 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc); in fsl_dma_alloc_descriptor()
470 INIT_LIST_HEAD(&desc->tx_list); in fsl_dma_alloc_descriptor()
471 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in fsl_dma_alloc_descriptor()
472 desc->async_tx.tx_submit = fsl_dma_tx_submit; in fsl_dma_alloc_descriptor()
473 desc->async_tx.phys = pdesc; in fsl_dma_alloc_descriptor()
481 * fsldma_clean_completed_descriptor - free all descriptors which
483 * @chan: Freescale DMA channel
493 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) in fsldma_clean_completed_descriptor()
494 if (async_tx_test_ack(&desc->async_tx)) in fsldma_clean_completed_descriptor()
499 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
500 * @chan: Freescale DMA channel
510 struct dma_async_tx_descriptor *txd = &desc->async_tx; in fsldma_run_tx_complete_actions()
513 BUG_ON(txd->cookie < 0); in fsldma_run_tx_complete_actions()
515 if (txd->cookie > 0) { in fsldma_run_tx_complete_actions()
516 ret = txd->cookie; in fsldma_run_tx_complete_actions()
530 * fsldma_clean_running_descriptor - move the completed descriptor from
532 * @chan: Freescale DMA channel
542 list_del(&desc->node); in fsldma_clean_running_descriptor()
548 if (!async_tx_test_ack(&desc->async_tx)) { in fsldma_clean_running_descriptor()
553 list_add_tail(&desc->node, &chan->ld_completed); in fsldma_clean_running_descriptor()
557 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); in fsldma_clean_running_descriptor()
561 * fsl_chan_xfer_ld_queue - transfer any pending transactions
562 * @chan : Freescale DMA channel
565 * LOCKING: must hold chan->desc_lock
575 if (list_empty(&chan->ld_pending)) { in fsl_chan_xfer_ld_queue()
585 if (!chan->idle) { in fsl_chan_xfer_ld_queue()
600 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); in fsl_chan_xfer_ld_queue()
601 list_splice_tail_init(&chan->ld_pending, &chan->ld_running); in fsl_chan_xfer_ld_queue()
604 * The 85xx DMA controller doesn't clear the channel start bit in fsl_chan_xfer_ld_queue()
608 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { in fsl_chan_xfer_ld_queue()
609 u32 mode; in fsl_chan_xfer_ld_queue() local
611 mode = get_mr(chan); in fsl_chan_xfer_ld_queue()
612 mode &= ~FSL_DMA_MR_CS; in fsl_chan_xfer_ld_queue()
613 set_mr(chan, mode); in fsl_chan_xfer_ld_queue()
620 set_cdar(chan, desc->async_tx.phys); in fsl_chan_xfer_ld_queue()
624 chan->idle = false; in fsl_chan_xfer_ld_queue()
628 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
630 * @chan: Freescale DMA channel
646 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { in fsldma_cleanup_descriptors()
649 * hardware channel, subsequent descriptors are either in in fsldma_cleanup_descriptors()
657 * channel is busy in fsldma_cleanup_descriptors()
659 if (desc->async_tx.phys == curr_phys) { in fsldma_cleanup_descriptors()
679 chan->common.completed_cookie = cookie; in fsldma_cleanup_descriptors()
683 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
684 * @chan : Freescale DMA channel
688 * Return - The number of descriptors allocated.
694 /* Has this channel already been allocated? */ in fsl_dma_alloc_chan_resources()
695 if (chan->desc_pool) in fsl_dma_alloc_chan_resources()
702 chan->desc_pool = dma_pool_create(chan->name, chan->dev, in fsl_dma_alloc_chan_resources()
705 if (!chan->desc_pool) { in fsl_dma_alloc_chan_resources()
707 return -ENOMEM; in fsl_dma_alloc_chan_resources()
715 * fsldma_free_desc_list - Free all descriptors in a queue
716 * @chan: Freescae DMA channel
719 * LOCKING: must hold chan->desc_lock
740 * fsl_dma_free_chan_resources - Free all resources of the channel.
741 * @chan : Freescale DMA channel
747 chan_dbg(chan, "free all channel resources\n"); in fsl_dma_free_chan_resources()
748 spin_lock_bh(&chan->desc_lock); in fsl_dma_free_chan_resources()
750 fsldma_free_desc_list(chan, &chan->ld_pending); in fsl_dma_free_chan_resources()
751 fsldma_free_desc_list(chan, &chan->ld_running); in fsl_dma_free_chan_resources()
752 fsldma_free_desc_list(chan, &chan->ld_completed); in fsl_dma_free_chan_resources()
753 spin_unlock_bh(&chan->desc_lock); in fsl_dma_free_chan_resources()
755 dma_pool_destroy(chan->desc_pool); in fsl_dma_free_chan_resources()
756 chan->desc_pool = NULL; in fsl_dma_free_chan_resources()
787 set_desc_cnt(chan, &new->hw, copy); in fsl_dma_prep_memcpy()
788 set_desc_src(chan, &new->hw, dma_src); in fsl_dma_prep_memcpy()
789 set_desc_dst(chan, &new->hw, dma_dst); in fsl_dma_prep_memcpy()
794 set_desc_next(chan, &prev->hw, new->async_tx.phys); in fsl_dma_prep_memcpy()
796 new->async_tx.cookie = 0; in fsl_dma_prep_memcpy()
797 async_tx_ack(&new->async_tx); in fsl_dma_prep_memcpy()
800 len -= copy; in fsl_dma_prep_memcpy()
805 list_add_tail(&new->node, &first->tx_list); in fsl_dma_prep_memcpy()
808 new->async_tx.flags = flags; /* client is in control of this ack */ in fsl_dma_prep_memcpy()
809 new->async_tx.cookie = -EBUSY; in fsl_dma_prep_memcpy()
811 /* Set End-of-link to the last link descriptor of new list */ in fsl_dma_prep_memcpy()
814 return &first->async_tx; in fsl_dma_prep_memcpy()
820 fsldma_free_desc_list_reverse(chan, &first->tx_list); in fsl_dma_prep_memcpy()
829 return -EINVAL; in fsl_dma_device_terminate_all()
833 spin_lock_bh(&chan->desc_lock); in fsl_dma_device_terminate_all()
839 fsldma_free_desc_list(chan, &chan->ld_pending); in fsl_dma_device_terminate_all()
840 fsldma_free_desc_list(chan, &chan->ld_running); in fsl_dma_device_terminate_all()
841 fsldma_free_desc_list(chan, &chan->ld_completed); in fsl_dma_device_terminate_all()
842 chan->idle = true; in fsl_dma_device_terminate_all()
844 spin_unlock_bh(&chan->desc_lock); in fsl_dma_device_terminate_all()
855 return -EINVAL; in fsl_dma_device_config()
859 /* make sure the channel supports setting burst size */ in fsl_dma_device_config()
860 if (!chan->set_request_count) in fsl_dma_device_config()
861 return -ENXIO; in fsl_dma_device_config()
864 if (config->direction == DMA_MEM_TO_DEV) in fsl_dma_device_config()
865 size = config->dst_addr_width * config->dst_maxburst; in fsl_dma_device_config()
867 size = config->src_addr_width * config->src_maxburst; in fsl_dma_device_config()
869 chan->set_request_count(chan, size); in fsl_dma_device_config()
875 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
876 * @chan : Freescale DMA channel
882 spin_lock_bh(&chan->desc_lock); in fsl_dma_memcpy_issue_pending()
884 spin_unlock_bh(&chan->desc_lock); in fsl_dma_memcpy_issue_pending()
888 * fsl_tx_status - Determine the DMA status
889 * @chan : Freescale DMA channel
902 spin_lock_bh(&chan->desc_lock); in fsl_tx_status()
904 spin_unlock_bh(&chan->desc_lock); in fsl_tx_status()
909 /*----------------------------------------------------------------------------*/
911 /*----------------------------------------------------------------------------*/
948 chan_dbg(chan, "irq: End-of-Chain link INT\n"); in fsldma_chan_irq()
953 * If it current transfer is the end-of-transfer, in fsldma_chan_irq()
954 * we should clear the Channel Start bit for in fsldma_chan_irq()
958 chan_dbg(chan, "irq: End-of-link INT\n"); in fsldma_chan_irq()
975 tasklet_schedule(&chan->tasklet); in fsldma_chan_irq()
986 spin_lock(&chan->desc_lock); in dma_do_tasklet()
989 chan->idle = true; in dma_do_tasklet()
994 spin_unlock(&chan->desc_lock); in dma_do_tasklet()
1007 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) in fsldma_ctrl_irq()
1008 : in_le32(fdev->regs); in fsldma_ctrl_irq()
1010 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); in fsldma_ctrl_irq()
1013 chan = fdev->chan[i]; in fsldma_ctrl_irq()
1018 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); in fsldma_ctrl_irq()
1035 if (fdev->irq) { in fsldma_free_irqs()
1036 dev_dbg(fdev->dev, "free per-controller IRQ\n"); in fsldma_free_irqs()
1037 free_irq(fdev->irq, fdev); in fsldma_free_irqs()
1042 chan = fdev->chan[i]; in fsldma_free_irqs()
1043 if (chan && chan->irq) { in fsldma_free_irqs()
1044 chan_dbg(chan, "free per-channel IRQ\n"); in fsldma_free_irqs()
1045 free_irq(chan->irq, chan); in fsldma_free_irqs()
1056 /* if we have a per-controller IRQ, use that */ in fsldma_request_irqs()
1057 if (fdev->irq) { in fsldma_request_irqs()
1058 dev_dbg(fdev->dev, "request per-controller IRQ\n"); in fsldma_request_irqs()
1059 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, in fsldma_request_irqs()
1060 "fsldma-controller", fdev); in fsldma_request_irqs()
1064 /* no per-controller IRQ, use the per-channel IRQs */ in fsldma_request_irqs()
1066 chan = fdev->chan[i]; in fsldma_request_irqs()
1070 if (!chan->irq) { in fsldma_request_irqs()
1072 ret = -ENODEV; in fsldma_request_irqs()
1076 chan_dbg(chan, "request per-channel IRQ\n"); in fsldma_request_irqs()
1077 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, in fsldma_request_irqs()
1078 "fsldma-chan", chan); in fsldma_request_irqs()
1080 chan_err(chan, "unable to request per-channel IRQ\n"); in fsldma_request_irqs()
1088 for (/* none */; i >= 0; i--) { in fsldma_request_irqs()
1089 chan = fdev->chan[i]; in fsldma_request_irqs()
1093 if (!chan->irq) in fsldma_request_irqs()
1096 free_irq(chan->irq, chan); in fsldma_request_irqs()
1102 /*----------------------------------------------------------------------------*/
1104 /*----------------------------------------------------------------------------*/
1113 /* alloc channel */ in fsl_dma_chan_probe()
1116 err = -ENOMEM; in fsl_dma_chan_probe()
1121 chan->regs = of_iomap(node, 0); in fsl_dma_chan_probe()
1122 if (!chan->regs) { in fsl_dma_chan_probe()
1123 dev_err(fdev->dev, "unable to ioremap registers\n"); in fsl_dma_chan_probe()
1124 err = -ENOMEM; in fsl_dma_chan_probe()
1130 dev_err(fdev->dev, "unable to find 'reg' property\n"); in fsl_dma_chan_probe()
1134 chan->feature = feature; in fsl_dma_chan_probe()
1135 if (!fdev->feature) in fsl_dma_chan_probe()
1136 fdev->feature = chan->feature; in fsl_dma_chan_probe()
1142 WARN_ON(fdev->feature != chan->feature); in fsl_dma_chan_probe()
1144 chan->dev = fdev->dev; in fsl_dma_chan_probe()
1145 chan->id = (res.start & 0xfff) < 0x300 ? in fsl_dma_chan_probe()
1146 ((res.start - 0x100) & 0xfff) >> 7 : in fsl_dma_chan_probe()
1147 ((res.start - 0x200) & 0xfff) >> 7; in fsl_dma_chan_probe()
1148 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { in fsl_dma_chan_probe()
1149 dev_err(fdev->dev, "too many channels for device\n"); in fsl_dma_chan_probe()
1150 err = -EINVAL; in fsl_dma_chan_probe()
1154 fdev->chan[chan->id] = chan; in fsl_dma_chan_probe()
1155 tasklet_setup(&chan->tasklet, dma_do_tasklet); in fsl_dma_chan_probe()
1156 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); in fsl_dma_chan_probe()
1158 /* Initialize the channel */ in fsl_dma_chan_probe()
1164 switch (chan->feature & FSL_DMA_IP_MASK) { in fsl_dma_chan_probe()
1166 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; in fsl_dma_chan_probe()
1169 chan->toggle_ext_start = fsl_chan_toggle_ext_start; in fsl_dma_chan_probe()
1170 chan->set_src_loop_size = fsl_chan_set_src_loop_size; in fsl_dma_chan_probe()
1171 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; in fsl_dma_chan_probe()
1172 chan->set_request_count = fsl_chan_set_request_count; in fsl_dma_chan_probe()
1175 spin_lock_init(&chan->desc_lock); in fsl_dma_chan_probe()
1176 INIT_LIST_HEAD(&chan->ld_pending); in fsl_dma_chan_probe()
1177 INIT_LIST_HEAD(&chan->ld_running); in fsl_dma_chan_probe()
1178 INIT_LIST_HEAD(&chan->ld_completed); in fsl_dma_chan_probe()
1179 chan->idle = true; in fsl_dma_chan_probe()
1181 chan->pm_state = RUNNING; in fsl_dma_chan_probe()
1184 chan->common.device = &fdev->common; in fsl_dma_chan_probe()
1185 dma_cookie_init(&chan->common); in fsl_dma_chan_probe()
1188 chan->irq = irq_of_parse_and_map(node, 0); in fsl_dma_chan_probe()
1190 /* Add the channel to DMA device channel list */ in fsl_dma_chan_probe()
1191 list_add_tail(&chan->common.device_node, &fdev->common.channels); in fsl_dma_chan_probe()
1193 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, in fsl_dma_chan_probe()
1194 chan->irq ? chan->irq : fdev->irq); in fsl_dma_chan_probe()
1199 iounmap(chan->regs); in fsl_dma_chan_probe()
1208 irq_dispose_mapping(chan->irq); in fsl_dma_chan_remove()
1209 list_del(&chan->common.device_node); in fsl_dma_chan_remove()
1210 iounmap(chan->regs); in fsl_dma_chan_remove()
1223 err = -ENOMEM; in fsldma_of_probe()
1227 fdev->dev = &op->dev; in fsldma_of_probe()
1228 INIT_LIST_HEAD(&fdev->common.channels); in fsldma_of_probe()
1231 fdev->regs = of_iomap(op->dev.of_node, 0); in fsldma_of_probe()
1232 if (!fdev->regs) { in fsldma_of_probe()
1233 dev_err(&op->dev, "unable to ioremap registers\n"); in fsldma_of_probe()
1234 err = -ENOMEM; in fsldma_of_probe()
1238 /* map the channel IRQ if it exists, but don't hookup the handler yet */ in fsldma_of_probe()
1239 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); in fsldma_of_probe()
1241 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); in fsldma_of_probe()
1242 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); in fsldma_of_probe()
1243 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; in fsldma_of_probe()
1244 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; in fsldma_of_probe()
1245 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; in fsldma_of_probe()
1246 fdev->common.device_tx_status = fsl_tx_status; in fsldma_of_probe()
1247 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; in fsldma_of_probe()
1248 fdev->common.device_config = fsl_dma_device_config; in fsldma_of_probe()
1249 fdev->common.device_terminate_all = fsl_dma_device_terminate_all; in fsldma_of_probe()
1250 fdev->common.dev = &op->dev; in fsldma_of_probe()
1252 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS; in fsldma_of_probe()
1253 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS; in fsldma_of_probe()
1254 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsldma_of_probe()
1255 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in fsldma_of_probe()
1257 dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); in fsldma_of_probe()
1264 * channel object. in fsldma_of_probe()
1266 for_each_child_of_node(op->dev.of_node, child) { in fsldma_of_probe()
1267 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { in fsldma_of_probe()
1270 "fsl,eloplus-dma-channel"); in fsldma_of_probe()
1273 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { in fsldma_of_probe()
1276 "fsl,elo-dma-channel"); in fsldma_of_probe()
1283 * If we have a per-controller interrupt, we prefer that to the in fsldma_of_probe()
1284 * per-channel interrupts to reduce the number of shared interrupt in fsldma_of_probe()
1289 dev_err(fdev->dev, "unable to request IRQs\n"); in fsldma_of_probe()
1293 dma_async_device_register(&fdev->common); in fsldma_of_probe()
1298 if (fdev->chan[i]) in fsldma_of_probe()
1299 fsl_dma_chan_remove(fdev->chan[i]); in fsldma_of_probe()
1301 irq_dispose_mapping(fdev->irq); in fsldma_of_probe()
1302 iounmap(fdev->regs); in fsldma_of_probe()
1315 dma_async_device_unregister(&fdev->common); in fsldma_of_remove()
1320 if (fdev->chan[i]) in fsldma_of_remove()
1321 fsl_dma_chan_remove(fdev->chan[i]); in fsldma_of_remove()
1323 irq_dispose_mapping(fdev->irq); in fsldma_of_remove()
1325 iounmap(fdev->regs); in fsldma_of_remove()
1337 chan = fdev->chan[i]; in fsldma_suspend_late()
1341 spin_lock_bh(&chan->desc_lock); in fsldma_suspend_late()
1342 if (unlikely(!chan->idle)) in fsldma_suspend_late()
1344 chan->regs_save.mr = get_mr(chan); in fsldma_suspend_late()
1345 chan->pm_state = SUSPENDED; in fsldma_suspend_late()
1346 spin_unlock_bh(&chan->desc_lock); in fsldma_suspend_late()
1351 for (; i >= 0; i--) { in fsldma_suspend_late()
1352 chan = fdev->chan[i]; in fsldma_suspend_late()
1355 chan->pm_state = RUNNING; in fsldma_suspend_late()
1356 spin_unlock_bh(&chan->desc_lock); in fsldma_suspend_late()
1358 return -EBUSY; in fsldma_suspend_late()
1365 u32 mode; in fsldma_resume_early() local
1369 chan = fdev->chan[i]; in fsldma_resume_early()
1373 spin_lock_bh(&chan->desc_lock); in fsldma_resume_early()
1374 mode = chan->regs_save.mr in fsldma_resume_early()
1376 set_mr(chan, mode); in fsldma_resume_early()
1377 chan->pm_state = RUNNING; in fsldma_resume_early()
1378 spin_unlock_bh(&chan->desc_lock); in fsldma_resume_early()
1391 { .compatible = "fsl,elo3-dma", },
1392 { .compatible = "fsl,eloplus-dma", },
1393 { .compatible = "fsl,elo-dma", },
1400 .name = "fsl-elo-dma",
1410 /*----------------------------------------------------------------------------*/
1412 /*----------------------------------------------------------------------------*/