15 #include "fsl-edma-common.h"
93 		if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr))  in fsl_edma3_enable_request()
94 			edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr);  in fsl_edma3_enable_request()
104 	struct edma_regs *regs = &fsl_chan->edma->regs;  in fsl_edma_enable_request()
110 	if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {  in fsl_edma_enable_request()
111 		edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);  in fsl_edma_enable_request()
112 		edma_writeb(fsl_chan->edma, ch, regs->serq);  in fsl_edma_enable_request()
130 		edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr);  in fsl_edma3_disable_request()
138 	struct edma_regs *regs = &fsl_chan->edma->regs;  in fsl_edma_disable_request()
144 	if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {  in fsl_edma_disable_request()
145 		edma_writeb(fsl_chan->edma, ch, regs->cerq);  in fsl_edma_disable_request()
146 		edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);  in fsl_edma_disable_request()
189 	u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;  in fsl_edma_chan_mux()
194 	chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;  in fsl_edma_chan_mux()
197 	if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP)  in fsl_edma_chan_mux()
200 	muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];  in fsl_edma_chan_mux()
203 	if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32)  in fsl_edma_chan_mux()
433 	 * big- or little-endian obeying the eDMA engine model endian,  in fsl_edma_set_tcd_regs()
487 	 * eDMA hardware SGs require the TCDs to be stored in little  in fsl_edma_fill_tcd()
832 	struct fsl_edma_engine *edma = fsl_chan->edma;  in fsl_edma_free_chan_resources()  local
838 	if (edma->drvdata->dmamuxs)  in fsl_edma_free_chan_resources()
870  * On the 32 channels Vybrid/mpc577x edma version, register offsets are
871  * different compared to ColdFire mcf5441x 64 channels edma.
875  * edma "version" and "membase" appropriately.
877 void fsl_edma_setup_regs(struct fsl_edma_engine *edma)  in fsl_edma_setup_regs()  argument
879 	bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64);  in fsl_edma_setup_regs()
881 	edma->regs.cr = edma->membase + EDMA_CR;  in fsl_edma_setup_regs()
882 	edma->regs.es = edma->membase + EDMA_ES;  in fsl_edma_setup_regs()
883 	edma->regs.erql = edma->membase + EDMA_ERQ;  in fsl_edma_setup_regs()
884 	edma->regs.eeil = edma->membase + EDMA_EEI;  in fsl_edma_setup_regs()
886 	edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ);  in fsl_edma_setup_regs()
887 	edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ);  in fsl_edma_setup_regs()
888 	edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI);  in fsl_edma_setup_regs()
889 	edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI);  in fsl_edma_setup_regs()
890 	edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT);  in fsl_edma_setup_regs()
891 	edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR);  in fsl_edma_setup_regs()
892 	edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT);  in fsl_edma_setup_regs()
893 	edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE);  in fsl_edma_setup_regs()
894 	edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR);  in fsl_edma_setup_regs()
895 	edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR);  in fsl_edma_setup_regs()
898 		edma->regs.erqh = edma->membase + EDMA64_ERQH;  in fsl_edma_setup_regs()
899 		edma->regs.eeih = edma->membase + EDMA64_EEIH;  in fsl_edma_setup_regs()
900 		edma->regs.errh = edma->membase + EDMA64_ERRH;  in fsl_edma_setup_regs()
901 		edma->regs.inth = edma->membase + EDMA64_INTH;  in fsl_edma_setup_regs()