dma/dw/regs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Driver for the Synopsys DesignWare AHB DMA Controller
5  * Copyright (C) 2005-2007 Atmel Corporation
6  * Copyright (C) 2010-2011 ST Microelectronics
14 #include <linux/io-64-nonatomic-hi-lo.h>
33  * Redefine this macro to handle differences between 32- and 64-bit
64 	/* per-channel registers */
89 	/* iDMA 32-bit support */
96 	/* per-channel configuration registers */
101 	/* top-level parameters */
108 	/* iDMA 32-bit support */
118 #define DW_PARAMS_NR_MASTER	11		/* number of AHB masters */
157 #define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */
162 #define DWC_CTLL_FC_M2M		(0 << 20)	/* mem-to-mem */
163 #define DWC_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
164 #define DWC_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
165 #define DWC_CTLL_FC_P2P		(3 << 20)	/* periph-to-periph */
166 /* plus 4 transfer types for peripheral-as-flow-controller */
202 #define DWC_CFGH_PROTCTL_DATA	(0 << 2)	/* data access - always set */
203 #define DWC_CFGH_PROTCTL_PRIV	(1 << 2)	/* privileged -> AHB HPROT[1] */
204 #define DWC_CFGH_PROTCTL_BUFFER	(2 << 2)	/* bufferable -> AHB HPROT[2] */
205 #define DWC_CFGH_PROTCTL_CACHE	(4 << 2)	/* cacheable  -> AHB HPROT[3] */
222 /* iDMA 32-bit support */
240 #define IDMA32C_CFGL_DST_BURST_ALIGN	(1 << 0)	/* dst burst align */
241 #define IDMA32C_CFGL_SRC_BURST_ALIGN	(1 << 1)	/* src burst align */
243 #define IDMA32C_CFGL_DST_OPT_BL		(1 << 20)	/* optimize dst burst length */
244 #define IDMA32C_CFGL_SRC_OPT_BL		(1 << 21)	/* optimize src burst length */
300 	return dwc->ch_regs;  in __dwc_regs()
304 	readl(&(__dwc_regs(dwc)->name))
306 	writel((val), &(__dwc_regs(dwc)->name))
345 	return dw->regs;  in __dw_regs()
349 	readl(&(__dw_regs(dw)->name))
351 	writel((val), &(__dw_regs(dw)->name))
354 	hi_lo_readq(&(__dw_regs(dw)->name))
356 	hi_lo_writeq((val), &(__dw_regs(dw)->name))
378 	 * silicon config may discard either or both...
388 #define lli_set(d, reg, v)		((d)->lli.reg |= cpu_to_le32(v))
389 #define lli_clear(d, reg, v)		((d)->lli.reg &= ~cpu_to_le32(v))
390 #define lli_read(d, reg)		le32_to_cpu((d)->lli.reg)
391 #define lli_write(d, reg, v)		((d)->lli.reg = cpu_to_le32(v))