dma/dw-axi-dmac/dw-axi-dmac.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5  * Synopsys DesignWare AXI DMA Controller driver.
19 #include "../virt-dma.h"
31 	/* maximum supported axi burst length */
73 	struct dw_axi_dma	*dw;  member
123 	return &dchan->dev->device;  in dchan2dev()
128 	return &chan->vc.chan.dev->device;  in chan2dev()
151 #define DMAC_ID			0x000 /* R DMAC ID */
152 #define DMAC_COMPVER		0x008 /* R DMAC Component Version */
153 #define DMAC_CFG		0x010 /* R/W DMAC Configuration */
154 #define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
155 #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
157 #define DMAC_CHSUSPREG		0x020 /* R/W DMAC Channel Suspend */
158 #define DMAC_CHABORTREG		0x028 /* R/W DMAC Channel Abort */
159 #define DMAC_INTSTATUS		0x030 /* R DMAC Interrupt Status */
160 #define DMAC_COMMON_INTCLEAR	0x038 /* W DMAC Interrupt Clear */
161 #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
162 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
163 #define DMAC_COMMON_INTSTATUS	0x050 /* R DMAC Interrupt Status */
164 #define DMAC_RESET		0x058 /* R DMAC Reset Register1 */
171 #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
172 #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
174 #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
175 #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
181 #define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
182 #define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
193 #define DMAC_APB_CFG		0x000 /* DMAC Apb Configuration Register */
194 #define DMAC_APB_STAT		0x004 /* DMAC Apb Status Register */
195 #define DMAC_APB_DEBUG_STAT_0	0x008 /* DMAC Apb Debug Status Register 0 */
196 #define DMAC_APB_DEBUG_STAT_1	0x00C /* DMAC Apb Debug Status Register 1 */
197 #define DMAC_APB_HW_HS_SEL_0	0x010 /* DMAC Apb HW HS register 0 */
198 #define DMAC_APB_HW_HS_SEL_1	0x014 /* DMAC Apb HW HS register 1 */
199 #define DMAC_APB_LPI		0x018 /* DMAC Apb Low Power Interface Reg */
200 #define DMAC_APB_BYTE_WR_CH_EN	0x01C /* DMAC Apb Byte Write Enable */
201 #define DMAC_APB_HALFWORD_WR_CH_EN	0x020 /* DMAC Halfword write enables */
226 /* DMAC CHAN BLOCKS */
332  * DW AXI DMA channel interrupts