dma/dw-axi-dmac/dw-axi-dmac.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5  * Synopsys DesignWare AXI DMA Controller driver.
19 #include "../virt-dma.h"
31 	/* maximum supported axi burst length */
58 	struct dma_device	dma;  member
123 	return &dchan->dev->device;  in dchan2dev()
128 	return &chan->vc.chan.dev->device;  in chan2dev()
155 #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
166 /* DMA channel registers offset */
171 #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
172 #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
174 #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
175 #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
181 #define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
182 #define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
196 #define DMAC_APB_DEBUG_STAT_1	0x00C /* DMAC Apb Debug Status Register 1 */
198 #define DMAC_APB_HW_HS_SEL_1	0x014 /* DMAC Apb HW HS register 1 */
203 #define UNUSED_CHANNEL		0x3F /* Set unused DMA channel to 0x3F */
213 #define INT_EN_POS			1
242 	DWAXIDMAC_ARWLEN_2		= 1,
332  * DW AXI DMA channel interrupts
336  * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
366 	DWAXIDMAC_IRQ_DMA_TRF		= BIT(1),