Lines Matching +full:axi +full:- +full:apb
1 /* SPDX-License-Identifier: GPL-2.0 */
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
5 * Synopsys DesignWare AXI DMA Controller driver.
19 #include "../virt-dma.h"
31 /* maximum supported axi burst length */
123 return &dchan->dev->device; in dchan2dev()
128 return &chan->vc.chan.dev->device; in chan2dev()
155 #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
171 #define CH_CTL_L 0x018 /* R/W Chan Control 00-31 */
172 #define CH_CTL_H 0x01C /* R/W Chan Control 32-63 */
174 #define CH_CFG_L 0x020 /* R/W Chan Configuration 00-31 */
175 #define CH_CFG_H 0x024 /* R/W Chan Configuration 32-63 */
181 #define CH_AXI_ID 0x050 /* R/W Chan AXI ID */
182 #define CH_AXI_QOS 0x058 /* R/W Chan AXI QOS */
192 /* These Apb registers are used by Intel KeemBay SoC */
193 #define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
194 #define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
195 #define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
196 #define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
197 #define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
198 #define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
199 #define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
200 #define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
332 * DW AXI DMA channel interrupts