dma/dw-axi-dmac/dw-axi-dmac.h

153 #define DMAC_CFG		0x010 /* R/W DMAC Configuration */
154 #define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
155 #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
157 #define DMAC_CHSUSPREG		0x020 /* R/W DMAC Channel Suspend */
158 #define DMAC_CHABORTREG		0x028 /* R/W DMAC Channel Abort */
160 #define DMAC_COMMON_INTCLEAR	0x038 /* W DMAC Interrupt Clear */
162 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
167 #define CH_SAR			0x000 /* R/W Chan Source Address */
168 #define CH_DAR			0x008 /* R/W Chan Destination Address */
169 #define CH_BLOCK_TS		0x010 /* R/W Chan Block Transfer Size */
170 #define CH_CTL			0x018 /* R/W Chan Control */
171 #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
172 #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
173 #define CH_CFG			0x020 /* R/W Chan Configuration */
174 #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
175 #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
176 #define CH_LLP			0x028 /* R/W Chan Linked List Pointer */
178 #define CH_SWHSSRC		0x038 /* R/W Chan SW Handshake Source */
179 #define CH_SWHSDST		0x040 /* R/W Chan SW Handshake Destination */
180 #define CH_BLK_TFR_RESUMEREQ	0x048 /* W Chan Block Transfer Resume Req */
181 #define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
182 #define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
185 #define CH_SSTATAR		0x070 /* R/W Chan Source Status Fetch Addr */
186 #define CH_DSTATAR		0x078 /* R/W Chan Destination Status Fetch Addr */
187 #define CH_INTSTATUS_ENA	0x080 /* R/W Chan Interrupt Status Enable */
188 #define CH_INTSTATUS		0x088 /* R/W Chan Interrupt Status */
189 #define CH_INTSIGNAL_ENA	0x090 /* R/W Chan Interrupt Signal Enable */
190 #define CH_INTCLEAR		0x098 /* W Chan Interrupt Clear */
329 #define CH_CFG2_H_PRIORITY_POS		20
383 	DWAXIDMAC_IRQ_SHADOWREG_ERR	= BIT(20),