dma/dw-axi-dmac/dw-axi-dmac.h

23 #define DMAC_MAX_BLK_SIZE	0x200000
147 #define COMMON_REG_LEN		0x100
148 #define CHAN_REG_LEN		0x100
151 #define DMAC_ID			0x000 /* R DMAC ID */
152 #define DMAC_COMPVER		0x008 /* R DMAC Component Version */
153 #define DMAC_CFG		0x010 /* R/W DMAC Configuration */
154 #define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
155 #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
156 #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
157 #define DMAC_CHSUSPREG		0x020 /* R/W DMAC Channel Suspend */
158 #define DMAC_CHABORTREG		0x028 /* R/W DMAC Channel Abort */
159 #define DMAC_INTSTATUS		0x030 /* R DMAC Interrupt Status */
160 #define DMAC_COMMON_INTCLEAR	0x038 /* W DMAC Interrupt Clear */
161 #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
162 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
163 #define DMAC_COMMON_INTSTATUS	0x050 /* R DMAC Interrupt Status */
164 #define DMAC_RESET		0x058 /* R DMAC Reset Register1 */
167 #define CH_SAR			0x000 /* R/W Chan Source Address */
168 #define CH_DAR			0x008 /* R/W Chan Destination Address */
169 #define CH_BLOCK_TS		0x010 /* R/W Chan Block Transfer Size */
170 #define CH_CTL			0x018 /* R/W Chan Control */
171 #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
172 #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
173 #define CH_CFG			0x020 /* R/W Chan Configuration */
174 #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
175 #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
176 #define CH_LLP			0x028 /* R/W Chan Linked List Pointer */
177 #define CH_STATUS		0x030 /* R Chan Status */
178 #define CH_SWHSSRC		0x038 /* R/W Chan SW Handshake Source */
179 #define CH_SWHSDST		0x040 /* R/W Chan SW Handshake Destination */
180 #define CH_BLK_TFR_RESUMEREQ	0x048 /* W Chan Block Transfer Resume Req */
181 #define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
182 #define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
183 #define CH_SSTAT		0x060 /* R Chan Source Status */
184 #define CH_DSTAT		0x068 /* R Chan Destination Status */
185 #define CH_SSTATAR		0x070 /* R/W Chan Source Status Fetch Addr */
186 #define CH_DSTATAR		0x078 /* R/W Chan Destination Status Fetch Addr */
187 #define CH_INTSTATUS_ENA	0x080 /* R/W Chan Interrupt Status Enable */
188 #define CH_INTSTATUS		0x088 /* R/W Chan Interrupt Status */
189 #define CH_INTSIGNAL_ENA	0x090 /* R/W Chan Interrupt Signal Enable */
190 #define CH_INTCLEAR		0x098 /* W Chan Interrupt Clear */
193 #define DMAC_APB_CFG		0x000 /* DMAC Apb Configuration Register */
194 #define DMAC_APB_STAT		0x004 /* DMAC Apb Status Register */
195 #define DMAC_APB_DEBUG_STAT_0	0x008 /* DMAC Apb Debug Status Register 0 */
196 #define DMAC_APB_DEBUG_STAT_1	0x00C /* DMAC Apb Debug Status Register 1 */
197 #define DMAC_APB_HW_HS_SEL_0	0x010 /* DMAC Apb HW HS register 0 */
198 #define DMAC_APB_HW_HS_SEL_1	0x014 /* DMAC Apb HW HS register 1 */
199 #define DMAC_APB_LPI		0x018 /* DMAC Apb Low Power Interface Reg */
200 #define DMAC_APB_BYTE_WR_CH_EN	0x01C /* DMAC Apb Byte Write Enable */
201 #define DMAC_APB_HALFWORD_WR_CH_EN	0x020 /* DMAC Halfword write enables */
203 #define UNUSED_CHANNEL		0x3F /* Set unused DMA channel to 0x3F */
204 #define DMA_APB_HS_SEL_BIT_SIZE	0x08 /* HW handshake bits per channel */
205 #define DMA_APB_HS_SEL_MASK	0xFF /* HW handshake select masks */
206 #define MAX_BLOCK_SIZE		0x1000 /* 1024 blocks * 4 bytes data width */
207 #define DMA_REG_MAP_CH_REF	0x08 /* Channel count to choose register map */
210 #define DMAC_EN_POS			0
217 #define DMAC_CHAN_EN_SHIFT		0
231 #define DMAC_CHAN_SUSP2_SHIFT		0
241 	DWAXIDMAC_ARWLEN_1		= 0,
264 	DWAXIDMAC_BURST_TRANS_LEN_1	= 0,
282 	DWAXIDMAC_CH_CTL_L_INC		= 0,
287 #define CH_CTL_L_SRC_MAST		BIT(0)
296 	DWAXIDMAC_HS_SEL_HW		= 0,
300 #define CH_CFG_H_TT_FC_POS		0
302 	DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC	= 0,
314 #define CH_CFG_L_SRC_MULTBLK_TYPE_POS	0
316 	DWAXIDMAC_MBLK_TYPE_CONTIGUOUS	= 0,
326 #define CH_CFG2_H_TT_FC_POS		0
364 	DWAXIDMAC_IRQ_NONE		= 0,
365 	DWAXIDMAC_IRQ_BLOCK_TRF		= BIT(0),
391 	DWAXIDMAC_IRQ_ALL		= GENMASK(31, 0)
395 	DWAXIDMAC_TRANS_WIDTH_8		= 0,