Lines Matching refs:iw
477 u8 iw; in interleave_ways_store() local
483 rc = ways_to_eiw(val, &iw); in interleave_ways_store()
1241 static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig) in check_interleave_cap() argument
1250 if (!test_bit(iw, &cxlhdm->iw_cap_mask)) in check_interleave_cap()
1268 ways_to_eiw(iw, &eiw); in check_interleave_cap()
1290 int parent_iw, parent_ig, ig, iw, rc, inc = 0, pos = cxled->pos; in cxl_port_setup_targets() local
1377 iw = cxl_rr->nr_targets; in cxl_port_setup_targets()
1378 rc = ways_to_eiw(iw, &eiw); in cxl_port_setup_targets()
1381 dev_name(port->uport_dev), dev_name(&port->dev), iw); in cxl_port_setup_targets()
1405 if (iw > 8 || iw > cxlsd->nr_targets) { in cxl_port_setup_targets()
1409 dev_name(&cxld->dev), iw, cxlsd->nr_targets); in cxl_port_setup_targets()
1414 if (cxld->interleave_ways != iw || in cxl_port_setup_targets()
1422 __func__, iw, ig, p->res); in cxl_port_setup_targets()
1435 rc = check_interleave_cap(cxld, iw, ig); in cxl_port_setup_targets()
1440 dev_name(&port->dev), iw, ig); in cxl_port_setup_targets()
1444 cxld->interleave_ways = iw; in cxl_port_setup_targets()
1452 dev_name(&port->dev), iw, ig); in cxl_port_setup_targets()
1645 int iw = cxld->interleave_ways; in cxl_region_attach_position() local
1649 if (dport != cxlrd->cxlsd.target[pos % iw]) { in cxl_region_attach_position()